Capacitor fabrication method

Details Capacitor fabrication method Capacitor fabrication method

2003-08-05

2004-08-31

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Making passive device

Stacked capacitor

C438S397000, C438S253000, C438S239000, C438S241000, C438S254000, C438S398000, C438S240000, C438S702000, C438S666000

Reexamination Certificate

active

06784068

ABSTRACT:

FIELD OF THE INVENTION
The present application relates generally to a fabrication method of semiconductor memory devices, and more particularly, to a capacitor fabrication method capable of enhancing the capacitance of a capacitor.
BACKGROUND OF THE INVENTION
The sharp increase of the recent demands for memory devices may be due to the advances in semiconductor fabrication technologies. In a semiconductor memory device, capacitors are generally utilized as the data storage means. The capacitance of a capacitor in a semiconductor device is variable based on the distance between two electrodes and the dielectric constant of a dielectric film inserted in between the two electrodes.
However, as the semiconductor memory devices are highly integrated, the high integration tends to decrease the area for the fabrication of the capacitors and thus leads to the reduced capacitor capacitance because of the decreased electrode area in the semiconductor device.
FIGS. 1A-1D
are sectional views illustrating a conventional fabrication method of a capacitor in a semiconductor memory device.
As shown in
FIG. 1A
, bit lines
3
are formed on a semiconductor substrate
1
, and the insulation spacers
4
are formed on the lateral portions of the bit lines
3
. Although not shown in the drawings, transistors including the dopant regions for the source/drain and for the gate electrodes are also fabricated on the semiconductor substrate
1
. The description relating to the transistor fabrication processes, which may occur before the formation of the bit lines, is omitted here.
Thereafter, several films are formed over the semiconductor substrate
1
, the bit lines
3
, and the insulation spacers
4
in the order of: an interlayer insulation film
5
, a silicon nitride film
6
, and a buffer film
7
as shown in FIG.
1
A. The buffer film
7
is made from an oxide film of Plasma Enhanced-Tetraethyl Orthosilicate (PE-TEOS) at a thickness of 500 to 1500 Å. Then a pattern of photosensitive film
20
is formed on the buffer film
7
to expose contact areas (not shown in
FIG. 1A
) for etching. The buffer film
7
, silicon nitride film
6
, and the interlayer insulation film
5
are etched according to the photosensitive film pattern as a mask to form contact holes h
1
as shown in FIG.
1
B. The photosensitive film pattern
20
is then removed.
A first polysilicon film is formed on a resultant structure including inside the contact holes h
1
, and then an etch-back or a Chemical Mechanical Polishing (CMP) is performed on the first polysilicon film to form conductive plugs
8
in the contact holes h
1
.
Then, as shown in
FIG. 1C
, a capacitor oxide film
9
such as a PE-PEOS or PSG film is formed on the resulting surface of the conductive plugs
8
and the buffer film
7
. A second polysilicon film
10
is formed on the oxide film
9
as a hard mask. A photosensitive film pattern (not shown) that defines a capacitor area is then formed on the second polysilicon film
10
.
The second polysilicon film
10
and the capacitor oxide film
9
are then etched by using the photosensitive pattern (not shown) as an etching barrier, up to the extent that the conductive plugs
8
are exposed in order to form contact holes h
2
for forming storage node electrodes (shown as
11
a
in FIG.
1
D). Then, a third polysilicon film
11
(which is used for forming the storage node electrodes shown as
11
a
in
FIG. 1D
) is formed on the surface of the resultant structure as shown in FIG.
1
C.
Now referring to
FIG. 1D
, an etch-back or a CMP is performed on the third polysilicon film
11
, which covers the walls of the contact holes h
2
, so that the storage node electrodes
11
a
are formed in the shape of cylinders on the conductive plugs
8
.
The second polysilicon film
10
(
FIG. 1C
) used for a hard mask and the oxide film
9
(
FIG. 1C
) are removed. Then, a Ta
2
O
5
dielectric film
12
and a TiN upper electrode
13
are sequentially formed on the storage node electrodes
11
a
. In order to reduce the contact resistance of the memory cell and the surrounding areas, the resultant structure including the capacitor TiN upper electrode
13
is heat treated at the temperature of 800-900° C. (
14
).
Fabrication of a semiconductor capacitor adopting a fine wiring process of 0.13 &mgr;m or less requires that the capacitor height be of at least 15,000 Å in order to enhance the active area of the storage node electrodes.
However, because the conventional fabrication method as described above deposits the oxide film as the buffer film
7
over the silicon nitride film
6
, deposits the silicon nitride film
6
as the etch stopper on the interlayer insulation film
5
, and then etches the above deposited films
5
,
6
, and
7
to form the contact holes h
1
, the conductive plugs
8
extends over the silicon nitride film
6
by a thickness of 500 to 1500 Å. This reduces the area of the storage node electrodes
11
a
in proportion to their thickness, while increasing the frequency of bridges between adjacent conductive plugs
8
, and causes electrical defects.
Also, in the fabrication method of the prior art, the Critical Dimension (CD) at the inner bottom of a cell is not ensured as a desired sufficient value after a mask process for formation of the storage node electrodes. As a result, after formation of the third polysilicon film
11
for storage node electrodes
11
a
and during formation of the Ta
2
O
5
dielectric film
12
and the TiN upper electrode
13
, step coverage defects may occur, thereby increasing leakage current from the capacitor.
Furthermore, the prior art method described above performs high temperature heat treatment at 800 to 900° C. after formation of the TiN upper electrode
13
of the capacitor so that oxidation occurs in the interface between the TiN upper electrode
13
and the Ta
2
O
5
dielectric film
12
during the heat treatment and oxygen vacancies are formed in the Ta
2
O
5
dielectric film
12
. This causes the deterioration of the Ta
2
O
5
dielectric film
12
and degrades the dielectric properties of the Ta
2
O
5
dielectric film
12
, while Cl
−
ions remaining in the upper electrode TiN film
13
causes the worsened leakage current of the capacitor.
SUMMARY OF THE INVENTION
Accordingly, an embodiment of the present invention has been made to solve the above-mentioned problems occurring in the prior art, and an object of the present invention is to provide a capacitor fabrication method in which conductive plugs are prevented from being erected over a silicon nitride film to increase the area of storage node electrodes thereby enhancing the capacitance of a capacitor.
Another object of the invention is to provide a capacitor fabrication method which can ensure the CD at the inner bottom of a memory cell to a desired sufficient value during formation of contact holes for storage node electrodes to improve the step coverage of a Ta
2
O
5
dielectric film and a TiN upper electrode.
Yet another object of the invention is to provide a capacitor fabrication method which can perform low temperature heat treatment to prevent dielectric property degradation of the Ta
2
O
5
dielectric film while reducing the ratio of Cl
−
ions remaining within the upper electrode TiN film thereby preventing leakage current from a capacitor.
In order to accomplish this object, a capacitor fabrication method according to an embodiment of the present invention comprises the following steps. A semiconductor substrate including at least one conductive plug is provided. A silicon nitride film and double capacitor oxide films are formed on the surface of the substrate having at least one conductive plug. The double capacitor oxide films have different wet etch rates. Dry etching and wet etching are sequentially performed to the selected portions of the double capacitor oxide films. Using the silicon nitride film as an etch stopper, at least one contact hole is formed by etching until the conductive plug is exposed. The contact hole is used for forming a storage node electrode. A silicon f

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