Capacitor employing both fringe and plate capacitance and...

Electricity: electrical systems and devices – Electrostatic capacitors – Fixed capacitor

Reexamination Certificate

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C361S306200, C029S025420

Reexamination Certificate

active

06661638

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention is directed, in general, to capacitor structures and, more specifically, to a capacitor, operable with a printed wiring board, that employs both fringe and plate capacitance, a method of manufacturing the same and a jack assembly, employing such capacitor, that is useful in enterprise structured cabling systems.
BACKGROUND OF THE INVENTION
Capacitors are among the oldest known electronic components. Those skilled in the art know and appreciate how capacitors may be used alone or in circuits of various types to in route, filter, modify and block electrical currents.
Capacitors are made up of two or more capacitor conductors that are separated by an insulator (or “dielectric” material). When a voltage difference exists between the two capacitor conductors, a corresponding electromagnetic field is formed. The electromagnetic field serves as a medium for containing electrical energy. The electrical energy can be drawn from the field via the conductors. The size and shape of the capacitor conductors and the extent to which the dielectric material electrically separates them from one another are factors in determining how much electrical energy can be stored in the electromagnetic field.
Printed wiring boards (PWBs) have long proven useful as substrates for circuits of all types. (PWBs may also be known as “printed circuit boards,” or “PCBs.” The terms are interchangeable for purposes of the present discussion). A PWB is often formed of a dielectric material on or in which are one or more layers of conductive material. The layer is typically arranged in a pattern to yield specific electrical conductors. Electrical components (including capacitors) can be mounted on the PWB and joined to the electrical conductors to form desired circuits.
Those skilled in the art know that capacitors can also be formed in the PWBs themselves, and quite inexpensively. Recalling that a capacitor is formed by at least two capacitor conductors separated by a dielectric material, it is straightforward to contemplate two ways to form a capacitor in a PWB.
The first way is to form two separate layers on or in the PWB and place a capacitor conductor on each layer. Viewing the PWB in a horizontal orientation, the capacitor conductors lie vertically over one another, and the dielectric material that separates the layers also separates the capacitor conductors. Capacitors thus formed are often called “plate capacitors,” because their capacitor conductors take advantage of the capacitance that exists between parallel planar conductors (“plate capacitance”).
The second way is to place the capacitor conductors on the same layer, but separate them laterally from one another. The gap that lies between the capacitor conductors serves as the dielectric material for the resulting capacitor. These capacitors are called “edge capacitors” or “fringe capacitors,” because the fringes of the capacitor conductors predominantly contribute to their capacitance.
A wide variety of today's applications require capacitors having highly accurate capacitance values. While discrete capacitor components can be employed in some of these applications, routing traces to and around discrete components may effectively prevent their use. Still other applications are severely cost- or space-sensitive and cannot justify the expense of discrete capacitor components.
At first glance, PWB-based capacitors of the type described above would seem readily to offer the answer to these types of applications, but limitations inherent in conventional PWB manufacturing processes have significantly complicated the fabrication of highly accurate PWB capacitors.
For example, any variation in plate size, thickness or separation can alter plate capacitance. Variations in the extent to which the plates are separated cause particularly dramatic changes in plate capacitance. Variations in gap have the same effect in fringe capacitors. Misregistration, etching depth variations, PWB laminate thickness variations, variations in conductive layer thickness and unpredictability of the dielectric constant of dielectric materials all contribute to potential inaccuracy and unacceptable rejection rates for such capacitors.
Accordingly, what is needed in the art is a fundamentally new architecture for PWB-based capacitors that is less sensitive to variations during fabrication than those of the prior art. What is also needed in the art is inexpensive communication circuitry that includes such capacitors.
SUMMARY OF THE INVENTION
To address the above-discussed deficiencies of the prior art, the present invention provides, for use in a printed wiring board, a capacitor, and a method of manufacturing the capacitor. In one embodiment, the capacitor includes: (1) first and second interdigitated finger sets, located on a first layer of the printed wiring board, that employ fringe capacitance to store electrical energy and together form a first capacitor conductor and (2) a second capacitor conductor, located on a second layer of the printed wiring board, that cooperates with the first capacitor conductor to employ plate capacitance to store further electrical energy.
The present invention therefore introduces a hybrid capacitor that employs both fringe and plate capacitance to provide an overall capacitance that is more tightly controllable and therefore suitable for use in circuits such as jack assemblies for computer network cables that require accurate and inexpensive capacitors.
In one embodiment of the present invention, the first and second interdigitated finger sets are square. The meaning of “square” will become evident upon inspection of one embodiment hereinafter to be illustrated and described. Those skilled in the pertinent art should understand, however, that other configurations are within the broad scope of the present invention.
In one embodiment of the present invention, the second capacitor conductor comprises third and fourth interdigitated finger sets. Thus, the second plate may itself employ fringe capacitance. In a more specific embodiment, the first and second interdigitated finger sets and the third and fourth interdigitated finger sets are laterally offset with respect to one another. Of course, the sets may be aligned over one another.
In one embodiment of the present invention, the capacitor further includes a third capacitor conductor, located on a third layer of the printed wiring board, that cooperates with the first and second capacitor conductors to employ the plate capacitance to store still further electrical energy. In a more specific embodiment, the third capacitor conductor comprises third and fourth interdigitated finger sets. In a still more specific embodiment, the capacitor further includes a fourth capacitor conductor, located on a fourth layer of the printed circuit board, that cooperates with the first, second and third capacitor conductors to employ the plate capacitance to store yet still further electrical energy. These and other embodiments will be illustrated and described in the Detailed Description that follows.
The foregoing has outlined, rather broadly, preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.


REFERENCES:
patent: 5583359 (1996-12-01), Ng et al.
patent: 9-186048 (1997-07-01), None

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