Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
2001-07-19
2003-09-23
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
C438S238000, C438S253000, C438S255000, C438S396000, C438S785000, C438S786000, C438S774000, C438S778000
Reexamination Certificate
active
06624038
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to a capacitor electrode having an uneven surface and used in a semiconductor device. More particularly, the present invention relates to manufacturing a capacitor which has a lower electrode having an uneven surface formed by using Hemispherical Grained Silicon (HSG-Si).
BACKGROUND OF THE INVENTION
A Dynamic Random Access Memory (DRAM) device is a semiconductor device in which data can be stored and retrieved randomly. As a memory cell of the DRAM device, a memory cell comprising one transfer transistor and one capacitor is widely used. This is because, such memory cell has a simple structure and is suitable for use in a semiconductor device having high integration degree.
According to an everlasting increase in an integration degree of a semiconductor device, a capacitor having three dimensional structure has been developed and utilized as a capacitor for such memory cell. This is because, in a semiconductor device having a high integration degree, it is necessary to enlarge a surface area of each capacitor electrode within a reduced capacitor area in the semiconductor device.
Until now, various structures for the above-mentioned capacitor electrode are proposed, and some of them are practically used. Among them, there is known a technology proposed in a paper entitled as “Hemispherical Grained Silicon (HSG-Si) Formation on In-Situ Phosphorous Doped Amorphous-Si Using the Speeding Method”, Solid State Devices and Materials, 1992, pp. 422-424. Hereafter, this technology is called HSG technology, and “Hemispherical Grained Silicon” is abbreviated to HSG-Si. The HSG technology is used as a technique for increasing a surface area of a lower electrode of a capacitor by forming unevenness on the surface of the lower electrode. It is considered that this technology is effective even in a DRAM device which has a memory capacity of 4 Giga-bits or so and in which fundamental design rule of a semiconductor element becomes approximately 0.13 &mgr;m.
There are many kinds of practical methods of forming a capacitor electrode by using the HSG technology. For example, Japanese patent laid-open publication No. 11-163274 proposes a method of efficiently forming uneven surface of an information storing electrode (hereafter, referred to as a lower electrode) of a capacitor by using HSG-Si.
With reference to the drawings, an explanation will be made on a conventional method of forming a lower electrode of a capacitor which is disclosed in the above-mentioned Japanese patent laid-open publication No. 11-163274.
FIG. 8
is a cross sectional view showing a schematic structure of a lower electrode of a conventional capacitor, that is, a conventional stacked capacitor.
FIG. 9
is a flow chart of manufacturing process showing a conventional method of forming unevenness on the surface of the lower electrode by using HSG-Si which comprises hemispherical grains of silicon.
First, with reference to
FIG. 8
, an explanation will be made on a lower electrode in which unevenness is formed on the surface thereof by using HSG-Si, that is, which has an uneven surface formed by using HSG-Si. A silicon substrate
101
is prepared. A diffusion layer
102
for capacitor, or a capacitor diffusion layer
102
, is formed in the silicon substrate
101
in the proximity of the surface of the silicon substrate
101
. An interlayer insulating film
103
which comprises a silicon oxide film is formed on whole area of the silicon substrate
101
. The interlayer insulating film
103
is selectively removed to form a contact hole
104
reaching the surface of the diffusion layer for capacitor
102
. Then, a lower electrode
105
is formed which electrically connects to the diffusion layer for capacitor
102
. Thereafter, a surface unevenness portion
106
is formed on the surface of the lower electrode
105
.
FIG. 8
shows a structure obtained in this way.
Next, with reference to
FIG. 9
, an explanation will be made in more detail on a conventional method of forming the lower electrode
105
having the above-mentioned surface unevenness portion
106
. After forming the contact hole
104
as mentioned above, an amorphous silicon film (hereafter referred to as a-Si film) is formed on the interlayer insulating film
103
such that the contact hole
104
is filled with material of the a-Si film. The a-Si film is deposited by using a reduced pressure chemical vapor deposition (CVD) method which uses mixed gas of monosilane (SiH
4
) and phosphine (PH
3
) or mixed gas of disilane (Si
2
H
6
) and phosphine (PH
3
), as reaction gas. The a-Si film is then microfabricated by using photolithography technology and dry etching technology. That is, the a-Si film is patterned to form the lower electrode
105
(step S
101
).
Then, the workpiece, that is, the semiconductor substrate, undergoes cleaning by chemical solution such as acid solution and the like (step S
102
). Thereby, a trace of heavy metal or particles are removed. Then, an oxide film, that is, a native oxide film, formed on the surface of the patterned a-Si film is removed (step S
103
). After these processing steps, the workpiece, that is, the silicon substrate
101
is inserted into a reaction furnace having high vacuum condition. In this reaction furnace, HSG nuclei are formed on the surface of the a-Si film which is patterned as mentioned above, and are heat treated to form a HSG-Si portion (step S
104
). The HSG-Si portion thus formed constitutes the surface unevenness portion
106
illustrated in FIG.
8
. Also, by this heat treatment, the patterned a-Si film is polycrystalized to become the lower electrode
105
which includes phosphorus impurities.
However, the above-mentioned conventional method of forming the lower electrode of a capacitor has the following disadvantage.
In a mass production process of DRAM's which uses lower electrodes having surface unevenness formed by using the HSG-Si, that is, hemispherical grains of silicon, as capacitor electrodes, the following disadvantage occurs. That is, there is a possibility that the surface unevenness is not formed uniformly on the surface of the lower electrode. If the unevenness is not formed uniformly, capacitance values of the capacitors vary, and may become out of standard. Therefore, there is a possibility that many defective devices are produced.
The inventor of this invention considered the causes of the above-mentioned disadvantage in detail. As a result thereof, the inventor found the following. In the above-mentioned heat treatment process or processes in which the HSG nuclei are formed on the surface of the a-Si film and further the HSG-Si portion is formed, moisture separates or is released from a semiconductor substrate, especially from an interlayer insulating film. The inventor found that the moisture separated from the semiconductor substrate has a great influence on the formation of the unevenness on the surface of the lower electrode. As will be mentioned in detail later, the moisture separated from the semiconductor substrate causes generation of Si-O bonds or couplings on the surface of the a-Si film. Unwanted objects including the Si-O bonds finally function so as to prevent formation of the HSG-Si. Thereby, densities of HSG nuclei on the surface of the a-Si film or diameters of hemispherical grains which comprise the HSG-Si may vary.
In a mass production line for semiconductor devices, semiconductor wafers on which many semiconductor devices are to be formed are often temporarily stored in a clean room until they undergo next process steps. While the semiconductor wafers are temporarily stored, moisture is absorbed into an interlayer insulating film comprising a silicon oxide film, in each of the semiconductor wafers, although the quantity of the moisture may be very small. It was also found that most of the moisture released from the interlayer insulating film during the above-mentioned process of forming the HSG-Si portion corresponds to the moisture absorbed into the interlayer insulating film while the semiconductor wafer i
Berry Renee R.
Katten Muchin Zavis & Rosenman
NEC Electronics Corporation
Nelms David
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