Capacitor designing method of MOS transistor

Details Capacitor designing method of MOS transistor Capacitor designing method of MOS transistor

1997-06-27

1999-10-12

Teska, Kevin J.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Converting, per se, of an ac input to corresponding dc at an...

327565, 257296, G06F 1750, H01L 27105, H01L 2500

Patent

active

059665181

ABSTRACT:
A method for designing to optimize a capacitor structure (channel length L, channel width W and number of division n) in a MOS transistor, in which the capacitor has a capacitance C and a gate-channel resistance R. A period from rising of a potential of a gate electrode to rising of potential of a diffusion layer is assumed as t2, a capacitance per unit area is assumed as K1 and a resistivity of the gate channel is assumed as K2 (S1), a period for propagating potential from a center portion of the gate channel to the end of a diffusion layer is assumed as t1 which is expressed by t1=0.55 CR (S2). Then, from C=K1.multidot.LW (S2), and R=K2.multidot.L/W (S3), t1=0.55 K1.multidot.K2 L.sup.2 (S4). Assuming t1=t2, L={t2/0.55K1.multidot.K2}.sup.1/2 is calculated (S5, 6), and W=C/K1.multidot.L is calculated (S7). From the capacitor region, a maximum value Wmax of the channel width is determined (S8) to derive number of division by rounding up the fraction below decimal point of quotient of W/Wmax.

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