Capacitor design in ESD circuits for eliminating current...

Details Capacitor design in ESD circuits for eliminating current... Capacitor design in ESD circuits for eliminating current...

2007-01-02

2007-01-02

Jackson, Stephen W. (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

Reexamination Certificate

active

10816745

ABSTRACT:
An electrostatic discharge (ESD) protection circuit for an integrated circuit (IC) is disclosed. The ESD protection circuit has a RC module having a resistor and capacitor connected in series; and a current dissipation module for dissipating the ESD, wherein the capacitor is formed by a thick native gate oxide of a transistor, and wherein the thick native gate oxide prevents leakage current formed therethrough so that to avoid leakage current through the current dissipation module during a normal operation of the IC.

REFERENCES:
patent: 4144634 (1979-03-01), Chang et al.
patent: 5452171 (1995-09-01), Metz et al.
patent: 5565790 (1996-10-01), Lee
patent: 6310379 (2001-10-01), Andresen et al.
patent: 6343045 (2002-01-01), Shau
patent: 6392860 (2002-05-01), Lin et al.
patent: 6812050 (2004-11-01), Ramappa
patent: 2002/0130390 (2002-09-01), Ker et al.
patent: 2002/0153570 (2002-10-01), Lin et al.
patent: 2003/0223166 (2003-12-01), Chen et al.

Affiliated with

Also associated with

Rating

Capacitor design in ESD circuits for eliminating current... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Capacitor design in ESD circuits for eliminating current..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Capacitor design in ESD circuits for eliminating current... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3814045