Capacitor-couple electrostatic discharge protection circuit

Details Capacitor-couple electrostatic discharge protection circuit Capacitor-couple electrostatic discharge protection circuit

1995-09-05

1997-05-20

Gaffin, Jeffrey A.

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

361111, H02H 900

Patent

active

056317930

ABSTRACT:
The present invention is related to a capacitor-couple electrostatic discharge (ESD) protection circuit for protecting an internal circuit and/or an output buffer of an IC from being damaged by an ESD current. The capacitor-couple ESD protection circuit according to the present invention includes an ESD bypass device for bypassing the ESD current, a capacitor-couple circuit for coupling a portion of voltage to the ESD bypass device, and a potential leveling device for keeping an ESD voltage transmitted for the internal circuit at a low potential level. By using the present ESD protection circuit, the snapback breakdown voltage can be lowered to protect the very thin gate oxide of the internal circuit especially in the submicron CMOS technologies.

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"Improving the ESD Failure Thresold of Silicided-MOS Output Transistor by Ensuring Uniform Current FLow", IEEE Transactions on Electron Devices, vol. 39, No. 2, Feb. 1992, authored by Thomas L. Polgreen et al.
"Dynamic Gate Coupling of NMOS for Efficient Output ESD Protection", IEEE, 1992, authored by Charvaka Duvvury et al.
"Achieving Uniform NMOS Device Power Distribution for Sub-micron ESD Reliability", IEEE, 1992, authored by Charvaka Duvvury et al.

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