Capacitor bias recovery methodology

Details Capacitor bias recovery methodology Capacitor bias recovery methodology

2000-07-21

2003-07-01

Faber, Alan T. (Department: 2651)

Dynamic magnetic information storage or retrieval

General recording or reproducing

Signal switching

C360S066000, C360S067000, C360S046000

Reexamination Certificate

active

06587296

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to disk drive circuits and, more particularly, to an apparatus, system and method for biasing a hard disk drive circuit.
BACKGROUND OF THE INVENTION
Hard disk drives such as the exemplary drive
10
illustrated in
FIG. 1
include a stack of magnetically coated platters
12
that are used for storing information. The magnetically coated platters
12
are mounted together in a stacked position through a spindle
14
which may be referred to as a platter stack. The platter stack is typically rotated by a motor that is referred to as a spindle motor or a servo motor (not shown). A space is provided between each platter to allow an arm
18
having a read/write head or slider
20
associated therewith to be positioned on each side of each platter
12
so that information may be stored and retrieved. Information is stored on each side of each platter
12
and is generally organized into sectors, tracks, zones, and cylinders.
Each of the read/write heads or sliders
20
are mounted to one end of the dedicated suspension arm
18
so that each of the read/write heads may be positioned as desired. The opposite end of each of the suspension arms
18
are coupled together at a voice coil motor
16
(VCM) to form one unit or assembly that is positionable by the voice coil motor. Each of the suspension arms
18
are provided in a fixed position relative to each other. The voice coil motor
16
positions all the suspension arms
18
so that the active read/write head
20
is properly positioned for reading or writing information. The read/write heads or sliders
20
may move from at least an inner diameter to an outer diameter of each platter
12
where data is stored. This distance may be referred to as a data stroke.
Hard disk drives also include a variety of electronic circuitry for processing data and for controlling its overall operation. This electronic circuitry may include a pre-amplifier, a read channel, a write channel, a servo controller, a motor control circuit, a read-only memory (ROM), a random-access memory (RAM), and a variety of disk control circuitry (not shown) to control the operation of the hard disk drive and to properly interface the hard disk drive to a system bus. The pre-amplifier may contain a read pre-amplifier and a write pre-amplifier that is also referred to as a write driver. The pre-amplifier may be implemented in a single integrated circuit or in separate integrated circuits such as a read pre-amplifier and a write pre-amplifier or write driver. The disk control circuitry generally includes a separate microprocessor for executing instructions stored in memory to control the operation and interface of the hard disk drive.
Hard disk drives perform write, read, and servo operations when storing and retrieving data. Generally, a write operation includes receiving data from a system bus and storing the data in the RAM. The microprocessor schedules a series of events to allow the information to be transferred from the RAM to the platters
12
through the write channel. Before the information is transferred, the read/write heads
20
are positioned on the appropriate track and the appropriate sector of the track is located. The data from the RAM is then communicated to the write channel as a digital write signal. The write channel processes the digital write signal and generates an analog write signal. In doing this, the write channel may encode the data so that the data can be more reliably retrieved later. The digital write signal may then be provided to an appropriate read/write head
20
after first being amplified by the pre-amplifier. Writing data to the recording medium or platter
12
is typically performed by applying a current to a coil of the head
20
so that a magnetic field is induced in an adjacent magnetically permeable core, with the core transmitting a magnetic signal across a spacing of the disk to magnetize a small pattern or digital bit of the media associated with the disk.
In a read operation, the appropriate sector to be read is located and data that has been previously written to the platters
12
is read. The appropriate read/write head
20
senses the changes in the magnetic flux and generates a corresponding analog read signal. The analog read signal is provided back to the electronic circuitry where a preamplifier circuit
32
amplifies the analog read signal. The amplified analog read signal is then provided to a read channel circuit
34
where the read channel conditions the signal and detects “zeros” and “ones” from the signal to generate a digital read signal. The read channel may condition the signal by amplifying the signal to an appropriate level using, for example, automatic gain control (AGC) techniques. The read channel may then filter the signal to eliminate unwanted high frequency noise, equalize the channel, perform the data recovery from the signal, and format the digital read signal. The digital read signal is then transferred from the read channel and is stored in the RAM (not shown). The microprocessor may then communicate to the host that data is ready to be transferred.
As seen in
FIG. 1
, many disk drive systems
10
utilize multiple heads
20
due to the multiple platters and use of both sides of the platter. When reading from a particular platter, the head associated therewith is biased at an optimal voltage via a bias current (wherein the unique head itself is the resistive load (RMR)). Therefore in order to bias each head in an optimal manner for read operations, the preamplifier circuit must supply the appropriate bias current to the respective head. Since each head does not exhibit the same resistance (e.g., 30&OHgr;, 45&OHgr;, etc.), the bias current provided by the preamplifier circuit must change depending on which head has been selected.
Therefore when a portion of data is segmented onto different platters and the data portion is being read, a head switch according to the prior art requires two write steps to a serial port register associated with the preamplifier circuit, wherein one step involves sending a serial, multi-bit code thereto indicating what head is the next or selected head, and another step involves writing a serial, multi-bit code to the serial port register indicating the appropriate bias current to employ for the desired head. Thus a head switch in the prior art required that two write steps to the serial port register be performed in a serial manner. Such sequencing negatively impacts the rate at which data can be read from the disk.
The reason that a prior art head switch requires two successive write steps to the serial port register may be further appreciated with respect to
FIG. 2
which illustrates an exemplary bias voltage circuit stage portion
50
of a preamplifier circuit. Bias voltage circuit
50
includes a bipolar transistor Q
1
which drives the head which is represented by a resistive load R
MR
(the value of which will vary from head to head from about 25&OHgr; to about 65&OHgr;). A g
m
amplifier operates to compare the voltages at nodes A and B produce an output signal associated therewith which drives an output node BIAS to charge or discharge capacitor C
1
. The charge on capacitor C
1
sets a bias voltage at the node BIAS which biases the transistor Q
1
, thereby setting the bias current through the head (R
MR
). The bias current through R
MR
influences the voltage at node B which is compared to a reference node A. Thus the influence of node B provides feedback via the g
m
amplifier and bias capacitor C
1
to adjust the bias current appropriately based on the reference voltage at node A. In addition, in order to improve a signal-to-noise ratio (S/N) the bias voltage circuit
50
includes a noise reduction capacitor C
2
which, although improving the S/N, slows the bias response of the circuit
50
by retarding the voltage response at node A, the negative impact of which will be discussed below.
When a head switch is to occur, a head select signal opens a switch S
1
which decouples the previously selected head a

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