Coded data generation or conversion – Analog to or from digital conversion – Digital to analog conversion
Reexamination Certificate
1997-08-12
2001-08-07
JeanPierre, Peguy (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Digital to analog conversion
C330S150000
Reexamination Certificate
active
06271784
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to a digital-to-analog converter using switched capacitors to produce a continuous time output.
A general trend in the integrated circuit industry is towards higher integration. Particularly in consumer markets such as portable communications, computer products, etc., higher levels of integration result in a smaller bill of materials, and therefore, power, area and cost savings. The performance parameters of circuits targeted for a highly integrated application specific integrated circuit (ASIC) can be very different from those of a general purpose circuit with the same function. Therefore, the design of such circuits should be approached differently. In the design of general purpose digital-to-analog converters (DACs), switched-capacitor charge redistribution structures have largely been avoided for a variety of reasons, including the need for a clock and the desire to avoid switching noise on the continuous time output of the DAC. Instead, attention has focused more heavily on switched-current or resistive ladder techniques.
In conventional standard mixed signal IC technology, polysilicon capacitors provide the best component matching per unit of area. It makes sense, therefore, to use poly—poly capacitors as the basic unit element in a high resolution converter. Especially in highly integrated mixed signal chips where a clock is readily available, a capacitor based DAC can save area and power over structures which rely on matching currents or voltages in transistors and/or resistors.
SUMMARY OF THE INVENTION
The invention provides a technique for implementing capacitor based charge-redistribution DACs suitable for small area, low power, and high accuracy implementations. The proposed architecture incorporates a capacitor array which implements the D/A function, a zeroth order sample and hold, and an output amplifier all into a single compact structure.
A digital-to-analog converter is provided which uses switched capacitors as the basic DAC elements. The use of switching capacitors provides excellent matching without sacrificing die area, and allows for very low-power operation. However, the architecture provides significant challenges when used in a continuous-time application requiring a smooth output.
Accordingly, the invention provides a digital-to-analog converter (DAC) including an array of switched input capacitors which store samples of charge proportional to a digital input signal, and an analog output circuit which combines the samples of charge to generate an output analog signal that is proportional to said digital input signal. The capacitors can be binary-weighted or otherwise capable of storing a binary representation of the digital input signal.
The output circuit includes a zeroth order sample-and-hold circuit having at least first and second amplifier stages. The first and second stages are cascaded together during a sample phase so that the analog output signal is generated on an output node, and is stored on a capacitor in a feedback path between the input and output of the second stage. The two stages are disconnected from one another during a hold phase so that the first stage is auto-zeroed and the second stage holds the analog output signal as a continuous time output.
In one aspect of the invention, the sample-and-hold circuit further includes a third amplifier stage cascaded between the first stage and a node between the feedback capacitor and the output of the second stage during a precharge phase so that parasitic capacitance at the node is driven to the value of the analog output signal to prevent undesirable glitching on the output node when the feedback capacitor is reconnected.
In another aspect of the invention, the first amplifier is configured as an inverting amplifier during the sample phase, and reconfigured as a non-inverting amplifier during the hold phase.
REFERENCES:
patent: 4404479 (1983-09-01), Toyomaki
patent: 4587443 (1986-05-01), Van De Plassche
patent: 4728811 (1988-03-01), Iida et al.
patent: 5258664 (1993-11-01), White
patent: 5708376 (1998-01-01), Ikeda
Ferguson, Jr. Paul F.
Lee Hae-Seung
Lynn Lapoe E.
Analog Devices Inc.
Jean-Pierre Peguy
Samuels , Gauthier & Stevens, LLP
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