Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2000-09-26
2003-05-13
Dang, Trung (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S534000, C257S309000, C438S128000, C438S381000
Reexamination Certificate
active
06563190
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a capacitor array of a semiconductor device having a plurality of capacitors and a method for fabricating the capacitor array. More particularly, the present invention relates to a capacitor array for preventing the crosstalk between adjacent capacitors in a semiconductor device and a method for fabricating the capacitor array.
As semiconductor devices have recently become more highly integrated, spacing between unit parts in semiconductor devices has greatly decreased. For example, a plurality of transistors and capacitors are included in a semiconductor memory device such as a dynamic random access memory (DRAM).
As the integration of the semiconductor memory device increases, spacing between the capacitors as well as between the gates of the transistors greatly decreases. This may cause various problems during operation, as well as during the fabrication of the semiconductor memory devices. For example, a decrease of the spacing between capacitors may disturb complete insulation between adjacent capacitors.
Moreover, crosstalk may sometimes occur between adjacent capacitors so that information cannot be accurately stored. Such crosstalk between adjacent capacitors greatly decreases the reliability of devices.
SUMMARY OF THE INVENTION
It is an objective of the present invention to provide a capacitor array including a plurality of capacitors that prevents crosstalk between adjacent capacitors during the operation of the device.
It is another objective of the present invention to provide a method for fabricating such a capacitor array.
To achieve the first objective, a capacitor array of a semiconductor device having a plurality of capacitors is provided. The capacitor array comprises a plurality of lower electrodes formed over a semiconductor substrate; one or more insulating layers formed between the adjacent lower electrodes, the insulating layers having pores of a low dielectric constant; a dielectric layer formed over the lower electrodes; and an upper electrode formed over the dielectric layer. The lower electrodes preferably each have a cylindrical shape. The insulating layers preferably comprise amorphous carbon, polyimide, or hybrid silicate-on-glass.
Alternately, a capacitor array of a semiconductor device having a plurality of capacitors may be provided. The capacitor array comprises a plurality of lower electrodes formed over a semiconductor substrate; one or more air gaps formed between the adjacent lower electrodes; a dielectric layer formed over the lower electrodes; and an upper electrode formed over the dielectric layer. The lower electrodes preferably each have a cylindrical shape.
To achieve the second objective, a method is provided for fabricating a capacitor array of a semiconductor device having a plurality of capacitors. The method comprises forming an insulating layer having a low dielectric constant over a semiconductor substrate; forming an etching stop layer over the insulating layer; forming a plurality of openings that expose a top surface of the semiconductor substrate at predetermined intervals by patterning the insulating layer and the etching stop layer; forming a lower electrode conductive layer over the etching stop layer and in the plurality of openings; removing a part of the lower electrode conductive layer to expose a surface of the etching stop layer, thereby forming a plurality of lower electrodes that are insulated from each other by the insulating layer; forming one or more air gaps between the plurality of lower electrodes by performing a heat treatment process at a predetermined temperature to remove the insulating layer from between the plurality of lower electrodes; forming a dielectric layer over the lower electrodes; and forming an upper electrode over the dielectric layer.
The insulating layer preferably comprises material that is completely thermally-decomposed at a temperature of 400° C. or less. More specifically, the insulating layer preferably comprises amorphous carbon, polyimide, or hybrid silicate-on-glass. The etching stop layer preferably comprises a Si
3
N
4
layer or a SiON layer. The lower electrodes are preferably each formed to have a cylindrical shape.
The method may further comprise forming a protective layer over the lower electrode conductive layer, within the openings, before removing a part of the lower electrode conductive layer; and removing the protective layer after forming the lower electrodes.
The protective layer is preferably formed by deposition of an oxide layer using a chemical vapor deposition method or a spin-on-glass method. The protective layer is preferably removed by a wet etching method. The removing of a part of the lower electrode conductive layer is preferably accomplished using a chemical-mechanical polishing process or an etch back process.
An alternate method for fabricating a capacitor array of a semiconductor device having a plurality of capacitors may also be provided. The method comprises forming an insulating layer having a low dielectric constant over a semiconductor substrate; forming an etching stop layer over the insulating layer; forming a plurality of openings that expose a top surface of the semiconductor substrate at predetermined intervals by patterning the insulating layer and the etching stop layer; forming a lower electrode conductive layer over the etching stop layer and in the openings; removing a part of the lower electrode conductive layer to expose a top surface of the etching stop layer, thereby forming lower electrodes that are insulated from each other by the insulating layer; forming pores in the insulating layer by performing a heat treatment process at a predetermined temperature; forming a dielectric layer over the lower electrodes; and forming an upper electrode over the dielectric layer.
The insulating layer preferably comprises a material that is partially thermally-decomposed at a temperature of 400° C. or less. More specifically, the insulating layer preferably comprises amorphous carbon, polyimide, or hybrid silicate-on-glass. The etching stop layer preferably comprises a Si
3
N
4
layer or a SiON layer. The lower electrodes are preferably each formed to have a cylindrical shape.
The method may further comprise forming a protective layer over the lower electrode conductive layer within the openings before removing a part of the lower electrode conductive layer; and removing the protective layer after forming the lower electrodes.
The protective layer is preferably formed by the deposition of an oxide layer using a chemical vapor deposition method or a spin-on-glass method. The protective layer is preferably removed by a wet etching method. The removing of a part of the lower electrode conductive layer is preferably accomplished by using a chemical-mechanical polishing process or an etch back process.
REFERENCES:
patent: 5000818 (1991-03-01), Thomas et al.
patent: 5461003 (1995-10-01), Havemann et al.
patent: 6150232 (2000-11-01), Chan et al.
patent: 6159842 (2000-12-01), Chang et al.
patent: 6187624 (2001-02-01), Huang
patent: 834916 (1998-04-01), None
patent: 06-302764 (1994-10-01), None
Kang Ho-kyu
Lee Hae-jeong
Dang Trung
Samsung Electronics Co,. Ltd
Volentine Francos P.L.L.C.
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