Coded data generation or conversion – Analog to or from digital conversion – Digital to analog conversion
Reexamination Certificate
2001-09-25
2002-12-17
Wamsley, Patrick (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Digital to analog conversion
C341S145000
Reexamination Certificate
active
06496131
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a capacitor-array D/A converter including a capacitor array and, in particular, to a capacitor arrangement for use in the capacitor array of the capacitor-array D/A converter.
An existing D/A (digital-to-analog) converter is used in various kinds of electronic circuits to convert a digital signal into a corresponding analog signal. With an improvement in performance of the electronic circuits, the D/A converter is required to have high accuracy.
For example, U.S. Pat. Nos. 5,949,362 and 6,236,346 disclose techniques for increasing the accuracy of the D/A converter, i.e., techniques for improving the linearity of a conversion characteristic upon conversion from a digital code into an analog voltage.
Referring to
FIG. 1
, description will be made of a current cell arrangement of a D/A converter disclosed in U.S. Pat. No. 5,949,362 as a first conventional technique for improving the linearity. A current cell matrix
25
comprises a first array
31
of a plurality of current source cells
32
positioned to the right of a dashed line
33
. The cells of the first array
31
extend in first and second directions perpendicular to each other. The current cell matrix
25
is provided with two-dimensional symmetrical control means
35
for operating predetermined current source cells of the first array
31
based upon at least a portion of digital input words and in a symmetrical sequence in both the first and the second directions with respect to a medial position of the first array. The medial position defines a centroid for the first array as shown by an imaginary point
39
. As an increasing number of current sources are switched, the current source cells labeled
1
-
31
are sequentially operated. Accordingly, the D/A converter illustrated in
FIG. 1
is less susceptible to variations in threshold voltage and current factor as may otherwise be caused by process gradients.
The first array
31
further comprises a plurality of second current source cells or LSB cells
32
a
labeled D
0
through D
4
in FIG.
1
. The two-dimensional symmetrical control means
35
further comprises LSB cell control means for operating the LSB current source cells
32
a
based upon predetermined least significant bits (LSBs) of the digital input words. The LSB current source cells (D
1
-D
4
) are positioned in a medial portion of the first array to reduce the influence of process gradients. The D/A converter
25
includes a second array
38
substantially similar to the first array
31
and located adjacent the first array
31
. The two-dimensional symmetrical control means
35
includes geometrical averaging means for operating the current source cells
32
in the first and second arrays
31
and
38
in pairs and in a substantially true mirror image sequence. For example, both cells of a pair may be connected to the same control signal and the output of each cell is half the desired combined output current.
Referring to
FIG. 2
, description will be made of a capacitor arrangement of a D/A converter which is disclosed in U.S. Pat. No. 6,236,346 as a second conventional technique for improving the linearity. Respective capacitance elements C are included in different cells
44
of a cell array
42
. The cells
44
have switch circuits
46
-
1
to
46
-
16
, respectively. Each switch circuit
46
has an input node connected to an output node (denoted by “X” in
FIG. 2
) of a corresponding one of the cells
44
. The output node is connected to a bottom plate of the capacitance element C in the cell. Each switch circuit
46
has three terminals, i.e., first through third terminals. The first terminals of the switch circuits
46
are connected in common to receive an input voltage VIN. The second terminals are connected in common to receive a negative reference voltage VSS. The third terminals are connected in common to receive a predetermined reference potential VREF. Each switch circuit
46
is controllable, in response to a selection signal S supplied thereto, to connect the input node to one of the first, the second, and the third terminals. The capacitance elements C in the different cells have top plates connected in common as an output VTOP of the D/A converter.
Referring to
FIG. 3
, five binary-weighted capacitors C
0
to C
4
are provided by the capacitance elements C in the different cells. The capacitor C
0
is provided by the capacitance element C of the cell
1
alone. The capacitor C
1
is provided by the capacitance element C of the cell
2
alone. The capacitor C
2
is provided by the capacitance elements C of the cells
3
and
4
connected in parallel. The capacitor C
3
is provided by the capacitance elements C of the cells
5
to
8
connected in parallel. The capacitor C
4
is provided by the capacitance elements C of the cells
9
to
16
connected in parallel. Therefore, the capacitance ratio of the capacitors C
0
to C
4
is 1:1:2:4:8.
For each row, each column, and each diagonal of the cell array
42
, the sum of respective selection-sequence positions of the cells is the same (
34
in this case). Referring to
FIG. 4
, a table shows an x-error and a y-error for each ordinal position in the selection sequence of the cells. For those cells that are selected in response to a given input code, the x-errors are summed to produce a total x-error &Sgr;x and the y-errors are summed to produce a total y-error &Sgr;y. By arranging the cell array in the configuration of a magic square as illustrated in
FIG. 2
, it is possible to realize a high-accuracy cell array circuit capable of two-dimensionally canceling an accumulation of graded and symmetrical errors in different rows and columns and to realize a high-accuracy D/A converter.
However, if the first conventional technique is similarly applied to a capacitor-array D/A converter or in case of the capacitor-array D/A converter according to the second conventional technique, the following disadvantages will arise.
As a first problem, the linearity of the D/A converter is deteriorated under the effect of a parasitic capacitance.
The reason is as follows. An output voltage of the D/A converter of a current cell matrix type according to the first conventional technique is determined exclusively by current values of the respective current source cells. On the other hand, an output voltage of the capacitor-array D/A converter is determined by capacitive voltage division from the sum of (1) capacitance values of the respective array capacitors, (2) capacitance values of coupling capacitors produced between the capacitors and connection lines for connecting the array capacitors and the switches, and (3) capacitance values of coupling capacitors produced between the array capacitors and connection lines for connecting the array capacitors to one another. In the first conventional technique, control is carried out by means of a mirror image (or symmetrical) arrangement and a mirror image (or symmetrical) sequence. Under such control, however, no more than the influence of variation in production accuracy of the current source cells is suppressed. Rather, the complexity in arrangement and control results in a complicated layout of the connection lines for transmission of control signals. Therefore, complicated coupling occurs between the array capacitors and the connection lines for connecting the array capacitors and the switches and between the array capacitors and the connection lines for connecting the array capacitors to one another. As a result, the linearity of the output voltage is degraded. In the second conventional technique, the capacitor cells are arranged in the configuration of the magic square. In this case also, no more than the influence of variation in production accuracy of capacitor cells is suppressed and the complexity in arrangement results in a complicated layout of the connection lines for the control signals. The linearity is deteriorated under the effect of the coupling capacitors in the similar manner as mentioned in conjunction with the first conventional technique.
Hayes & Soloway PC
Wamsley Patrick
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