Electricity: electrical systems and devices – Electrostatic capacitors – Fixed capacitor
Reexamination Certificate
2002-04-30
2003-05-20
Dinkins, Anthony (Department: 2831)
Electricity: electrical systems and devices
Electrostatic capacitors
Fixed capacitor
C361S311000, C257S310000
Reexamination Certificate
active
06567260
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a capacitor, and is applicable to a capacitor as a storage node of a semiconductor memory, for example.
2. Description of the Background Art
As the integration density of a device has increased, a chip size has decreased. Accordingly, each size of storage nodes of a semiconductor memory, as well as each interval between the storage nodes, has been reduced. In developing a DRAM with a chip of a small size, it is required that a capacitor have an increased capacitance.
To meet the foregoing requirement, various attempts have been made, including: increasing an aspect ratio of a hole in which a storage node is to be formed (hereinafter, referred to as a “storage node hole”); increasing the dielectric constant of a dielectric film used for storing an electric charge in a storage node (hereinafter, referred to as a “capacitor dielectric film”); and reducing the thickness of a capacitor dielectric film. As one example of such capacitor dielectric film, a Ta
2
O
5
film has been proposed.
FIG. 14
is a schematic view showing an example of a structure of a conventional DRAM. An isolating oxide film
102
is provided in a surface of a semiconductor substrate
101
of silicon, for example, and partitions an element region
114
. Further, a gate wiring
104
which is surrounded by an insulative gate surrounding film
103
and functions as a transfer gate is provided on a surface of the isolating oxide film
102
and an exposed surface of the semiconductor substrate
101
. The gate wiring
104
extends in a direction perpendicular to the plane of the drawing. The gate surrounding film
103
shown in
FIG. 14
includes a gate insulating film provided under the gate wiring
104
in the element region
114
. Meanwhile, a source/drain region provided in the surface of the semiconductor substrate
101
in the element region
114
is omitted in the drawing.
A first interlayer insulating film
105
has a bilayer structure formed of layers
105
a
and
105
b.
A conductive connection part
106
is formed of a plug
106
a
and a landing pad
106
b.
The connection part
106
passes through the first interlayer insulating film
105
and connects the element region
114
to a rough semiconductor film
108
which has a rough surface and functions as one of opposite electrodes of a storage node
120
.
A partition wall
107
for forming a storage node hole is selectively provided on the first interlayer insulating film
105
. The rough semiconductor film
108
is provided both on a side face of the partition wall
107
and a surface of the first interlayer insulating film
105
which includes an exposed surface of the connection part
106
.
A cell plate
110
functioning as the other of the opposite electrodes of the storage node
120
faces the rough semiconductor film
108
with a capacitor dielectric film
109
interposed therebetween. As the capacitor dielectric film
109
, a Ta
2
O
5
film can be employed. Further, a second interlayer insulating film
111
, a metal interconnect layer
112
and a passivation film
113
are sequentially formed on the cell plate
110
in this order.
Increase in an aspect ratio of the storage node
120
results in increase in a possibility that the coverage of the rough semiconductor film
108
provided by the capacitor dielectric film
109
at the bottom of the storage node
120
, in other words, near the surface of the first interlayer insulating film
105
, is degraded. The foregoing possibility is further increased particularly when a diameter of each of particles contributing to the roughness of the rough surface of the rough semiconductor film
108
is increased in order to increase the capacitance of the storage node
120
. The reason for it is that also an aspect ratio of each clearance provided by the particles in the rough surface of the rough semiconductor film
108
is increased so that the capacitor dielectric film
109
can not easily enter among the particles. A poor coverage of the rough semiconductor film
108
by the capacitor dielectric film
109
causes a problem that the amount of leakage current in the bottom of the storage node
120
is more likely to increase.
Further, there is another problem that use of a sintering process accelerates the increase of leakage current. In forming a transistor in the element region
114
, it is not unusual that a heat treatment (a sintering process) at a temperature of 400° C. for 15 minutes while using a hydrogen atmosphere, for example, is performed in order to improve an interface state of an interface between the gate insulating film and a channel region of the transistor to be formed. During the heat treatment, reduction reaction of the Ta
2
O
5
film employed as the capacitor dielectric film
109
occurs. As a result, the effective film thickness of the capacitor dielectric film
109
is reduced, which invites further increase in the amount of leakage current.
SUMMARY OF THE INVENTION
The present invention addresses the problems associated with the background art as noted above. To solve the problems, an object of the present invention is to provide a technique for reducing a leakage current of a capacitor.
According to the present invention, a capacitor includes a bottom, a side face, a first electrode, a dielectric film and a second electrode. The side face forms a storage node hole in conjunction with the bottom. The surface of the first electrode is roughened at the side face and the bottom. The surface is roughened finer at the bottom than at the side face. The second electrode faces the first electrode with the dielectric film interposed therebetween.
The first electrode at the bottom of the storage node hole is roughened fine, so that the dielectric film can easily enter among the roughness in that portion. As a result, it is possible to increase the capacitance by the roughness of the first electrode in the side face of the storage node hole, while reducing a leakage current by the roughness of the first electrode in the bottom of the storage node hole.
According to the present invention, a capacitor includes a plurality of storage nodes. Each of the plurality of storage nodes has a first electrode, a dielectric film and a second electrode. The first electrode is provided on a bottom and a side face of a storage node hole. The second electrode faces the first electrode with the dielectric film interposed therebetween. The plurality of storage nodes are arranged checkerwise in a plan view.
An aspect ratio of the storage node hole can be reduced without increasing the cell size of a memory comprising a plurality of the capacitors or necessarily reducing the capacitance. As a result, it is possible to improve a coverage of the first electrode provided by the dielectric film, thereby to reduce a leakage current.
According to the present invention, a capacitor includes a first electrode, a dielectric film and a second electrode. The first electrode is provided on a bottom and a side face of a storage node hole. The second electrode faces the first electrode with the dielectric film interposed therebetween. The dielectric film includes a Ta
2
O
5
film having a thickness of 6 nm or larger.
The amount of leakage current normalized based on the capacitance is drastically reduced as compared with an instance where a Ta
2
O
5
film with a thickness of 6 nm or smaller is used, even if a sintering process using a hydrogen atmosphere is performed. As a result, it is possible to ensure the effective film thickness of the dielectric film and reduce a leakage current in a semiconductor memory comprising the capacitor and a semiconductor element, as well as to suppress the interface state of the semiconductor element.
This and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5110752 (1992-05-01), Lu
patent: 5266514 (1993-11-01), Tuan et
Dinkins Anthony
Mitsubishi Denki & Kabushiki Kaisha
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