Capacitor and method of formation and a memory cell formed there

Details Capacitor and method of formation and a memory cell formed there Capacitor and method of formation and a memory cell formed there

1994-01-18

1995-04-11

Thomas, Tom

Fishing, trapping, and vermin destroying

437 52, 437 60, 437919, H01L 27108

Patent

active

054057965

ABSTRACT:
A capacitor for use in a memory cell (10). A transistor is formed overlying a substrate (10). The transistor has a first current electrode (16) and a second current electrode (18). The current electrodes (16 and 18) are separated by a channel region. A gate electrode (26) is formed overlying the channel region and is physically separated from the channel region by a gate dielectric layer (24). A plug region (32) is formed overlying and electrically connected to the first current electrode (16). An annular high-permittivity dielectric region (33) is formed overlying the transistor and is formed from a high-permittivity dielectric layer (36). A first capacitor electrode is formed via a conductive region (38"), and a second capacitor electrode is formed via a conductive region (38'). The memory cell (10) can be formed as a non-volatile memory cell or a DRAM cell depending upon various properties of the annular high-permittivity dielectric region (33).

REFERENCES:
patent: 4987470 (1991-01-01), Suzuki et al.
patent: 5045899 (1990-05-01), Arimoto
patent: 5046043 (1991-09-01), Miller et al.
patent: 5047815 (1991-09-01), Yasuhira et al.
patent: 5106775 (1992-04-01), Kaga et al.
patent: 5150276 (1992-09-01), Gonzalez et al.
patent: 5155573 (1992-10-01), Abe et al.
patent: 5185282 (1993-02-01), Lee et al.

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