Capacitor and method for manufacturing the same

Details Capacitor and method for manufacturing the same Capacitor and method for manufacturing the same

2001-08-03

2002-11-19

Reichard, Dean A. (Department: 2831)

Electricity: electrical systems and devices

Electrostatic capacitors

Fixed capacitor

C361S321100, C361S306100, C361S311000, C438S240000, C438S250000, C257S295000

Reexamination Certificate

active

06483691

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a capacitor and a method for manufacturing the same wherein a dielectric layer is made of ferroelectric material or a material of high dielectric constant and which is formed on an insulating film on a surface of a substrate. More particularly, it relates to a capacitor capable of preventing dispersion of the metallic component(s) of the dielectric material into the insulating film or a semiconductor layer or preventing occurrence of cracks in the dielectric material, by patterning a lower electrode and by making the dielectric layer of the capacitor directly contact with the insulating film, and which is further capable of preventing influences of adhesion of the electrode or interdiffusion also in case the electrode is electrically connected to the semiconductor layer via the plug within the contact hole formed in the insulating film.
BACKGROUND ART
In forming a plurality of dielectric capacitors on a same substrate such as a semiconductor substrate, it is necessary to perform patterning of a formed electrode or a dielectric layer. It is possible to employ a method as illustrated in FIG.
8
(
a
) in which an upper electrode
6
, a dielectric layer
5
and a lower electrode
4
are processed in a lump. The example as illustrated in FIG.
8
(
a
) is a sectional explanatory view of an example in which an insulating film
2
is formed on a semiconductor substrate
1
, and electric connection is achieved with a semiconductor layer formed below the insulating film
2
via a plug
7
formed within a contact hole
11
formed in the insulating film
2
, the plug being made of conductive layer of, for instance, poly-silicon. In this method, it is required to sequentially perform etching of the three layers by using the same mask while processing thereof is difficult in view of selection of etching conditions and others, and etching damages may be formed at side wall portions that undergo etching that will cause degradations in capacitor characteristics.
It is known for a method to perform separate patterning of the three layers of the lower electrode
4
, the dielectric layer
5
and the upper electrode
6
as illustrated in FIG.
8
(
b
) in order to avoid such etching damages. However, in performing separate patterning of the three layers, it will be required for mask alignments for each of the layers, and alignment margins A and B, which depend on alignment accuracies for forming the etching pattern, will further be required. It is therefore necessary to secure a larger area than an actual area of the capacitor and will cause an increase in cell area (chip area).
In order to solve such problems, it would be possible to employ a method as illustrated in FIG.
8
(
c
) in which the lower electrode
4
is patterned prior to forming the dielectric layer
5
, and in which the dielectric layer
5
is either refrained from etching of the dielectric layer
5
or etching thereof is performed for an area that is larger than the lower electrode
4
, whereupon the upper electrode
6
is formed. Such a method will be effective in achieving smaller etching margin and less etching damages. However, since SiO
2
is usually used as the insulating film
2
formed on the substrate to form a base for the capacitor, the dielectric film
5
will directly contact the SiO
2
film in this method. This method is further disadvantaged in that a weak point (see point C) is formed on an edge portion of the lower electrode
4
at which the dielectric layer
5
is thin. In such a case, though troubles can be eliminated if patterning would be performed to make the upper electrode
6
face the lower electrode
4
to be identical in size, it may also be the case that it is used as a common plate (wiring) so that short deficiencies of both electrodes
4
,
6
are apt to occur.
In case the dielectric layer of the capacitor is made of ferroelectric material or a material of high dielectric constant, Pb or Ti of the ferroelectric layer may be diffused into the SiO
2
film and may further be diffused into the semiconductor layer formed downward thereof upon direct contact of the ferroelectric layer with SiO
2
to thus cause degradations not only of the capacitor but also of element characteristics of the semiconductor elements, and it may, in some cases, cause to crack in the dielectric layer.
On the other hand, it is suggested in Japanese Patent Application Unexamined Publication No. 7-99290 (1995) that for the purpose of preventing interactive reaction, which may be caused upon contact of a ferroelectric layer of a ferroelectric capacitor with a silicon-containing layer, a titanium dioxide layer or an oxide layer of magnesium zirconium, tantalum or the like shall be formed at portions that come in contact with the ferroelectric layer. However, oxides of titanium, magnesium, zirconium, tantalum or the like exhibit extremely poor workability and thus lead to a drawback that it is difficult to perform precise patterning owing to time-consuming processing through dry etching or adhesion of liberated heavy metal, which is a constitutive element thereof, on the surface exposed by etching. It is thus of disadvantage that they cannot be used particularly for the case as illustrated in FIG.
8
(
a
) in which a contact hole is formed in the insulating film on which the capacitor is to be formed for electric connection with a plug formed therein.
When manufacturing a ferroelectric capacitor in which the lower electrode is connected to the semiconductor layer via the plug formed in the contact hole of the insulating film, interactive reaction may be caused between the ferroelectric layer and poly-silicon, which is a material usually used for forming the plug, to cause degradations in capacitor characteristics or degradations in element characteristics of semiconductor elements in case the lower electrode is made of Pt, which exhibits superior orientation for the ferroelectric layer, and thus makes constitutive elements such as Pb, Zr or O of the ferroelectric layer easily pass through. Moreover, adhesion between the lower electrode made of Pt, which is suitable for forming the ferroelectric film, and the plug is not necessarily favorable and may cause in worsened ohmic contact.
The present invention has been made for the purpose of solving such problems, and it is an object thereof to provide a capacitor and a method for manufacturing the same which is capable of improving workability through dry etching while preventing diffusion and immersion of constitutive elements of the ferroelectric material or material of high dielectric constant such as Ti or Pb into the SiO
2
film or the semiconductor layer.
It is another object of the present invention to provide a capacitor and a method for manufacturing the same that is of a structure in which weak points are hardly occurring in the dielectric layer.
It is still another object of the present invention to provide a capacitor of a structure in which preventing the interaction between the dielectric layer and the SiO
2
film or the semiconductor layer may be achieved while improving adhesion between the lower electrode of the capacitor and the plug formed within a contact hole of the insulating film and preventing the interaction between the dielectric layer and the plug through the lower electrode.
It is still another object of the present invention to provide a method for manufacturing a capacitor in which the oxide of high melting point metal such as Ti, Ta or Zr exhibiting high barrier effects with respect to the ferroelectric layer may be interposed between the dielectric layer made of ferroelectric or the like and the insulating film made of SiO
2
film or the like as a barrier layer without the necessity of patterning, also in case the lower electrode is electrically connected to the underlying layer through the contact hole.
DISCLOSURE OF THE INVENTION
The capacitor according to the present invention comprises; a lower electrode formed on a silicon oxide film, a dielectric layer formed on the lower electrode and made of fer

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