Electricity: electrical systems and devices – Electrostatic capacitors – Fixed capacitor
Reexamination Certificate
2002-03-22
2003-11-11
Reichard, Dean A. (Department: 2831)
Electricity: electrical systems and devices
Electrostatic capacitors
Fixed capacitor
C361S306100, C361S311000, C361S313000, C361S321500
Reexamination Certificate
active
06646860
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a capacitor to be used in analog circuits of semiconductor integrated circuits, and a method for fabricating the capacitor.
In semiconductor integrated circuits (ICs), capacitors have been so far generally used to cut direct current components in high-frequency regions. The capacitors have been required to be built in ICs for the purpose of cost reduction by external parts decrease, terminal number decrease, etc. The capacitors have been required to be built in ICs for easy countermeasures to noises.
Conventionally, a capacitor built in an IC is always accompanied by a parasitic capacitance. The parasitic capacitance is an error of an intrinsic capacitance of the capacitor which causes accuracy reduction. Although the capacitor itself consumes no electric power, a parasitic capacitance part consumes useless electric power. Accordingly, a large parasitic capacitance requires the higher driving capacity for the driving amplifier of the IC. A result is an undesirable chain of a higher power consumption. Thus, the parasitic capacitance of capacitors built in ICs have been a barrier to high-speed achievements of the ICs.
For the end of decreasing such parasitic capacitance, process developments have been made to replace MOS (Metal-Oxide-Semiconductor) capacitors by two-layer poly capacitors, MIM (Metal-Insulator-Metal) capacitors, etc. which will be described later. Contrivances for reducing the influence of the parasitic capacitance to the circuits have been made in circuits and layouts.
FIGS. 13A and 13B
are diagrammatic views of conventional capacitors, which show the structure thereof.
FIG. 13A
is a sectional view of 2-layer poly capacitor, which shows the structure thereof.
FIG. 13B
is a sectional view of an MIM capacitor, which shows the structure thereof.
As shown in
FIG. 13A
, the 2-layer poly capacitor comprises a lower layer electrode
104
and an upper layer electrode
106
of a polycrystal silicon film formed in an inter-layer insulation film
102
on a silicon substrate
100
. As shown in
FIG. 13B
, the MIM capacitor comprises a lower layer electrode
108
and an upper layer electrode
110
of a metal, such as aluminium, copper, titanium nitride or others, formed in an inter-layer insulation film on a silicon substrate
100
. Recently, the MIM capacitor, which is superior in the parasitic capacitance and parasitic resistance, is becoming dominant.
In a capacitor built in an IC, the parasitic capacitance tends to combine with the lower electrode, which is thought to be caused by its structural reason. Accordingly, when the capacitor is built in the IC, the lower layer electrode is formed on the side where the circuit is less vulnerable to the parasitic capacitance. That is, the lower layer electrode is used on the side where a potential is fixed. The upper layer electrode is used generally on the side where the circuit is vulnerable to the parasitic capacitance.
An example of the application of the conventional MIM capacitor to an IC will be explained by means of a case that the conventional MIM capacitor is applied to a sample and hold circuit with reference to
FIGS. 14A and 14B
.
FIG. 14A
is a sectional view of the MIM capacitor used in the sample and hold circuit.
FIG. 14B
is an upper side view of the MIM capacitor, which shows the structure thereof. The sectional view shown in
FIG. 14A
is along the line A-A′ in FIG.
14
B. The capacitor shown in
FIGS. 14A and 14B
includes a plurality of inter-layer insulation films formed between interconnection layers, etc., but the inter-layer insulation films will be referred to an inter-layer insulation film
124
as a whole in the explanation with reference to
FIGS. 14A and 14B
.
As shown in
FIG. 14A
, in the sample and hold circuit, an input unit
112
for an input voltage to be inputted to, and an output unit
114
for an output voltage to be outputted are interconnected via a switch
116
. A node
118
is provided between the switch
116
and the output unit
114
and is connected to a capacitor
120
. The side of the capacitor
120
opposed to the node
116
is grounded, and the potential is fixed. The capacitor
120
is provided by an MIM capacitor.
As shown in
FIG. 14A
, the MIM capacitor comprises a lower layer electrode/lower interconnection layer
126
which functions as a lower layer electrode of the capacitor, formed on a substrate
122
with an inter-layer insulation film
124
formed therebetween. An upper interconnection layer
132
is formed above the upper layer electrode
128
, connected to the upper electrode
128
through a via layer
130
formed in the inter-layer insulation film
124
.
In the sample and hold circuit, the node
118
has a high impedance for a period of time of an operation when the capacitor
120
has a parasitic capacitance, which makes it easy to superimpose noises via the parasitic capacitance. This is a cause for errors. Then, in a case that an MIM capacitor is used in such sample and hold circuit, as shown in
FIG. 14A
, the upper interconnection layer
128
is connected to the node
118
. The lower electrode/lower interconnection layer
126
is grounded with a potential fixed. The lower electrode of the MIM capacitor, which tends to have parasitic capacities, has a potential fixed, whereby the influence of the parasitic capacitance has been reduced as much as possible.
As described above, in order to reduce or remove parasitic capacities of capacitors built in ICs, the approaches have been made from various viewpoints of process developments, circuit designs, etc.
However, the above-described conventional capacitor has failed sufficiently reduce the parasitic capacitance. There is a demerit that the structure of the conventional MIM capacitor is vulnerable to influences of external noises.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a capacitor which can drastically reduce parasitic capacitance, which is a cause for lower accuracy of the capacitor, useless electric power consumption, etc. in comparison with the conventional capacitor, and can shield off external noises, and a method for fabricating the capacitor.
According to one aspect of the present invention, there is provided a capacitor comprising: a lower layer electrode formed on a substrate with a first insulation film therebetween; an upper layer electrode opposed to the lower layer electrode with a second insulation film therebetween; and a lower interconnection layer formed between the substrate and the lower layer electrode and electrically connected to the upper layer electrode.
According to another aspect of the present invention, there is provided a capacitor comprising: a lower layer electrode formed on a substrate with a first insulation film therebetween; an upper layer electrode opposed to the lower layer electrode with a second insulation film therebetween; a lower interconnection layer formed between the substrate and the lower layer electrode and electrically connected to the upper layer electrode; and an upper interconnection layer formed on the upper layer electrode with a third insulation film therebetween and electrically connected to the lower interconnection layer.
According to farther another aspect of the present invention, there is provided a method for fabricating a capacitor comprising the steps of forming a lower layer electrode on a substrate with a first insulation film therebetween, and forming an upper layer electrode opposed to the lower layer electrode with a second insulation film therebetween, the method further comprising the step of: forming a lower interconnection layer between the substrate and the lower layer electrode and electrically connected to the upper layer electrode.
According to farther another aspect of the present invention, there is provided a method for fabricating a capacitor comprising the steps of: forming a lower layer electrode on a substrate with a first insulation film therebetween; forming an upper layer electrode opposed to the lower layer electrode wit
Gotoh Kunihiko
Takaramoto Toshiharu
Armstrong Westerman & Hattori, LLP
Fujitsu Limited
Ha Nguyen T.
Reichard Dean A.
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