Capacitor and method for fabricating the same

Details Capacitor and method for fabricating the same Capacitor and method for fabricating the same

1999-12-07

2001-09-04

Tsai, Jey (Department: 2812)

Semiconductor device manufacturing: process

Having magnetic or ferroelectric component

C438S253000, C438S240000

Reexamination Certificate

active

06284551

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a capacitor and a method for fabricating the same, which can simplify a fabrication process and reduce parasitic capacitances between signal lines, which improves a device reliability.
2. Background of the Related Art
In general, there are the stack type and the trench type in the capacitors, and in turn there are the fin type and the cylinder type in the stack type. In order to secure a capacitance effectively, in general cylinder type of capacitors are used in 64MDRAM. However, in a case of 256MDRAM which is involved in a severe dimensional reduction, it is a general trend that an HSG (Hemi-Spherical Grain) is applied to a related art structure of the 256MDRAM for increasing a capacitance capacity.
A related art method for fabricating a capacitor will be explained with reference to the attached drawings. FIGS.
1
A~
1
G illustrate sections showing the steps of a related art method for fabricating a capacitor.
Referring to
FIG. 1A
, a first insulating layer
12
is formed on a semiconductor substrate
11
having a cell transistor formed thereon, and bitlines
13
are formed on the first insulating layer
12
, selectively. A second insulating layer
14
is formed on the first insulating layer
12
inclusive of the bitline
13
, planarized, and a silicon nitride film
15
is formed on the second insulating layer
14
. A third insulating layer
16
is formed on the silicon nitride film
15
, and a first photoresist
17
is coated on the third insulating layer
16
, and subjected to patterning by exposure and development, to define a storage node contact region. As shown in
FIG. 1B
, the patterned first photoresist
17
is used as a mask in etching the third insulating layer
16
, the silicon nitride film
15
, the second insulating layer
14
, and the first insulating layer
12
selectively, to form a storage node contact hole
18
which exposes a surface of the substrate
11
As shown in
FIG. 1C
, after the first photoresist
17
is removed, an insulating sidewall
19
is formed on an inside surface of the storage node contact hole
18
. Then, a conductive material, such as polysilicon, for storage node contact is deposited on the third insulating layer
16
inclusive of the substrate, and planarized until the third insulating layer is exposed, to form a storage node contact
18
a
which is a conductive material stuffed in the storage node contact hole
18
. As shown in
FIG. 1D
, a conductive material
20
for a capacitor lower electrode is formed on the third insulating layer
16
inclusive of the storage node contact
18
a
. And, a second photoresist
17
a
is coated on the conductive material
20
for capacitor lower electrode, and subjected to patterning by exposure and development, to define a capacitor lower electrode region. As shown in
FIG. 1E
, the patterned second photoresist
17
a
is used as a mask in etching the conductive material
20
for capacitor lower electrode selectively to remove the conductive material selectively, to form a capacitor lower electrode
20
a
electrically connected to the storage node contact
18
a
. As shown in
FIG. 1F
, the third insulating layer
16
is removed by wet etching to expose the silicon nitride film
15
. And, a capacitor dielectric film
21
is deposited on the capacitor lower electrode
20
a
inclusive of the silicon nitride film
15
. Then, as shown in
FIG. 1G
, upon formation of a capacitor upper electrode
22
on the capacitor dielectric film
21
, the related art method for fabricating a capacitor is completed.
In the meantime, in the related art, if a ferroelectric film is used as a capacitor dielectric film, in order to prevent oxidization of the polysilicon of the storage node contact due to a strong oxidizing atmosphere, formation of an oxidization prevention film on the capacitor node contact is required.
However, the related art method for fabricating a capacitor has the following problems.
First, the parasitic capacitance between the storage node contact and the bitline taking place inevitably for devices 256MDRAM class and over with very small sized device affects a device reliability, greately.
Second, in formation of a cylinder type capacitor, if a surface is extended down to a bottom surface of a capacitor lower electrode, a coupling parasitic capacitance is occurred between the capacitor upper electrode and the bitline with a dielectric film inbetween.
Third, if the capacitor dielectric film is formed of a ferroelectric material, formation an additional oxidizing prevention film is required for preventing the polysilicon of the storage node contact from being oxidized by the strong oxidizing atmosphere, resulting in a complicated fabrication process.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a capacitor and a method for fabricating the same that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a capacitor and a method for fabricating the same, which can simplify a fabrication process, and prevent parasitic capacitances between various signals lines, that improves a device reliability.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the capacitor includes a first insulating layer formed on a substrate, a bitline patterned on the first insulating layer, a second insulating layer formed on the bitline, a first electrode formed on the second insulating layer with slopes at both sides, a dielectric film formed on the first electrode, a node contact formed on one side of the first electrode and in contact with the substrate, and a second electrode formed on the dielectric film and connected with the node contact, electrically.
In other aspect of the present invention, there is provided a method for fabricating a capacitor, including the steps of (1) forming a first insulating layer on a substrate, and patterning a bitline on the first insulating layer, (2) forming a second insulating layer on an entire surface inclusive of the bitline, (3) depositing a first conductive material on the second insulating layer, (4) etching the first conductive material to form a first electrode with a sloped etch surface, (5) depositing a dielectric film on the first electrode, (6) etching the second insulating layer and the first insulating layer in succession to form a contact hole exposing the substrate, (7) depositing and etching a second conductive in the contact hole, to form a node contact, and (8) depositing and etching a third conductive material on the node contact, to form a second electrode.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5420070 (1995-05-01), Matsuura et al.
patent: 5583068 (1996-12-01), Jones, Jr. et al.
patent: 6174735 (2001-01-01), Evans

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