Semiconductor device manufacturing: process – Having magnetic or ferroelectric component
Reexamination Certificate
2003-07-08
2004-11-02
Graybill, David E. (Department: 2827)
Semiconductor device manufacturing: process
Having magnetic or ferroelectric component
Reexamination Certificate
active
06812042
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor device; and, more particularly, to a capacitor for use in a semiconductor device and a method for fabricating a having the same.
DESCRIPTION OF RELATED ARTS
With using a ferroelectric material for a capacitor used in a semiconductor memory device, a development of the device has been progressed in order to overcome a refresh limit of a prior dynamic random access memory (DRAM) device and use a large quantity of memory. A nonvolatile ferroelectric random access memory (FeRAM) is expected to be a promising memory device in near future due to some advantages of saving information even if a power is off and competing with the prior DRAM device in terms of an operation speed.
The nonvolatile memory device using the ferroelectric material inputs a signal by controlling a polarization direction controlled by applying an electric field, wherein a remnant polarization formed after the electric field is cut off is used for saving a digital signal
1
or
0
.
Usually, SrBi
2
Ta
2
O
9
(SBT) or Pb(Zr, Ti)O
3
(PZT) film is used as a ferroelectric material for the FeRAM device. The ferroelectric material has a dielectric constant for a few hundreds to a few thousands at a room temperature and two types of stable remnant polarization status. Therefore, it is expected to apply a ferroelectric material film to the nonvolatile memory device.
In addition, a new ferroelectric material such as Bi
4-x
La
x
Ti
3
O
12
(BLT) and Bi
4
Ti
3
O
12
(BTO) have advantageous properties such as a superior reliability of the SBT and a low crystallization temperature of the PZT including a strong polarizability.
FIG. 1A
shows a cross sectional view illustrating a conventional ferroelectric memory device.
As shown, an isolation layer
12
predetermining an active region is formed on a semiconductor substrate
11
. A stacked structure of a gate oxide layer
13
and a word line
14
is formed on the semiconductor substrate
11
thereafter. Source/drain regions
15
A and
15
B are formed on both right and left sides adjacent to the word line
14
.
In addition, a first interfacial insulation layer
16
is formed on a transistor containing the word line
14
and the source/drain regions
15
A and
15
B. A bit line
18
is connected to one source/drain region
15
A through a bit line contact
17
contacting to one source/drain region
15
A by passing through the first interfacial insulation layer
16
.
A second interfacial insulation layer
19
containing the bit line
18
is formed on an entire upper area of the transistor and a storage node contact
20
is formed thereon, wherein the first interfacial insulation layer
16
and the second interfacial insulation layer
19
are penetrated together in order to make the storage node contact
20
connected to the other source/drain region
15
B.
A lower electrode
21
which should be connected to the storage node contact
20
is formed. Also, a planerized isolating insulation layer
22
for a separation of the lower electrode
21
from an adjacent electrode encompasses the lower electrode
21
. Next, a ferroelectric layer
23
covers the insolating insulation layer
22
and the lower electrode
21
, wherein the ferroelectric layer
21
uses the BTO or BLT and is formed only on a cell region.
An upper electrode
24
is formed on the formed ferroelectric layer
23
. A capacitor structure shown in
FIG. 1A
is named as a merged top plate (MTP).
However, the BTO or BLT capacitor has a disadvantage that the BTO or BLT ferroelectric material is operated at a high speed in a high temperature ambiance, a data fatigue occurs generally and drastically, so that it causes a device data failure. Furthermore, the data fatigue brings about deoxidization of titanium (Ti) ions. More specifically, the Ti ion deoxidization is caused by a charge impact externally applied. In addition, the Ti ion deoxidization causes some defects, which are concentrated or diffused into an electrode interface, and consequently, those defects suppress a dipole formation. From this, the polarizability of the BTO or BLT is reduced. Eventually, the film impaired with such defects within its interface is prone to damage because a conductor phenomenon increases an applied electric field to the interface.
FIG. 1B
is a graph showing a result of a reliability test for BLT film fabricated by a conventional method, wherein a horizontal axis represents a switching cycle, a vertical axis denotes a polarization value (P*~P{circumflex over ( )}), and +dP and −dP mean a positive polarization value and a negative polarization value, respectively.
FIG. 1C
is a graph showing an attenuation range of the reliability in a numerical value, wherein an horizontal axis denotes a test temperature and a vertical axis describes a polarization value (P*−P{circumflex over ( )}).
Referring to
FIG. 1B
, a remnant polarization is drastically reduced at about 125° C. (▴, ▾). More precisely, the reliability is drastically reduced at a high switching cycle point when data is rapidly used for a long time. In addition, the reliability is reduced at the high switching cycle point even at a room temperature.
Referring to
FIG. 1C
, the polarization value is drastically reduced as a measurement temperature gets high. More precisely, the polarization value (P*−P{circumflex over ( )}) is abruptly reduced from about 18 &mgr;C/cm
2
to less than about
10 &mgr;C/cm
2
.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a method for fabricating a ferroelectric memory device capable of suppressing a defect generation caused by a charge impact.
In accordance with an aspect of the present invention, there is provided the ferroelectric memory device, including: a semiconductor substrate on which a transistor is formed; a lower electrode on the interfacial insulation layer, which is connected to a source/drain region of the transistor through a contact penetrating the interfacial insulation layer; an isolating insulation layer on the interfacial insulation layer, which has a planerized surface exposing a surface of the lower electrode and encompasses the lower electrode; a ferroelectric layer covering the isolating insulation layer and lower electrode; an oxygen vacancy compensation layer on the ferroelectric layer compensating an oxygen vacancy caused by a deoxidization of a composition of the ferroelectric layer; and an upper electrode formed on the oxygen vacancy compensation layer.
In addition, there is provided the method for fabricating the ferroelectric memory device, including: forming the interfacial insulation layer on the semiconductor substrate; forming a stack pattern of the lower electrode and a hard mask in order on the interfacial insulation layer; forming the isolating insulation layer on an entire surface having the stack pattern; planerizing the isolating insulation layer until exposing a surface of the hard mask; removing the hard mask by using a liquid chemical; forming the ferroelectric layer on an entire surface having the lower electrode exposed after the hard mask is removed; forming the oxygen vacancy compensation layer on the ferroelectric layer; forming a conductive layer for the upper electrode on the oxygen vacancy compensation layer; and pattering the conductive layer and the oxygen vacancy compensation layer consecutively.
REFERENCES:
patent: 5780886 (1998-07-01), Yamanobe
patent: 6063639 (2000-05-01), Kim et al.
patent: 6420740 (2002-07-01), Zhang et al.
patent: 6555429 (2003-04-01), Matsui et al.
Kim Nam-Kyeong
Kweon Soon-Yong
Yeom Seung-Jin
Graybill David E.
Hynix / Semiconductor Inc.
Jacobson & Holman PLLC
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