Capacitor and memory structure and method

Details Capacitor and memory structure and method Capacitor and memory structure and method

1998-03-27

2001-03-06

Saadat, Mahshid (Department: 2815)

Semiconductor device manufacturing: process

Making passive device

Stacked capacitor

C438S396000, C438S253000, C438S255000, C438S261000, C438S565000, C257S298000

Reexamination Certificate

active

06197653

ABSTRACT:

BACKGROUND OF THE INVENTION
The invention relates to electronic semiconductor devices, and, more particularly, to capacitor structures and fabrication methods for such structures.
Increasing demand for semiconductor memory and competitive pressures requires higher density integrated circuit dynamic random access memories (DRAMs) based on one-transistor plus one-capacitor memory cell. But down scaling capacitors with the standard silicon oxide and nitride dielectrics presents problems including decreasing quantity of charge stored in a cell. Consequently, DRAM manufacturers are investigating alternative dielectrics to increase capacitor dielectric constant and alternative cell structures to increase capacitor area. For example, U.S. Pat. No.5,554,557 discloses a DRAM cell with a fence-shaped capacitor having a rugged polysilicon lower electrode to increase the capacitor area. The patent discloses deposition of rugged polysilicon by silane decomposition at 560° C. and a pressure about 200 mTorr to yield a layer of hemispherical grains of maximum thickness of 50-150 nm. Then conformally deposits a dielectric of silicon nitride, oxide
itride/oxide, or tantalum pentoxide, and complete the capacitor with a top electrode of deposited polysilicon.
Ino et al., Rugged Surface Polycrystalline Silicon Film Deposition and its Application in a Stacked Dynamic Random Access Memory Capacitor Electrode, 14 J.Vac.Sci.Tech.B 751 (1996) describes (FIG. 14) capacitors with rugged polysilicon for layer thicknesses in the range of 40-150 nm with the optimal at a 100 nm thickness.
SUMMARY OF THE INVENTION
The present invention provides an HSG silicon (rugged polysilicon) layer of thickness less than 40 nm but with surface area increase of least 2 by high nucleation density deposition plus gas phase grain shape enhancement and doping in a single furnace operation. Preferred embodiment rugged polysilicon forms a (dynamic memory cell) capacitor electrode which is surface area enhanced and the capacitor dielectric is deposited without electrode exposure to oxygen sources.
This has the advantages of high packing density memory cells using processes compatible with standard silicon integrated circuit fabrication.


REFERENCES:
patent: 5266514 (1993-11-01), Tuan et al.
patent: 5691228 (1997-11-01), Ping et al.
patent: 5798280 (1998-08-01), Mathews et al.
Hirohito Watanabe et al., Hemispherical Grained Si Formation on in-situ Phosphorus Doped Amorphous-Si Slectrode for 256 Mb DRAM's Capacitor, IEEE Electron Devices, vol. 42, No. 7, pp. 1247-1253, Jul. 1995.

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