Capacitor

Electricity: electrical systems and devices – Electrolytic systems or devices – Liquid electrolytic capacitor

Reexamination Certificate

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C361S516000, C361S517000

Reexamination Certificate

active

06661644

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a multilayer capacitor that is used on the secondary side of a power supply smoothing circuit and on the periphery of a CPU of a computer. More particularly, the present invention relates to a capacitor having small equivalent series inductance (hereinafter referred to as “ESL”) and small equivalent series resistance (hereinafter referred to as “ESR”) at high frequencies.
2. Related Background Art
Recently, with the digitization of electronic equipment, miniaturized capacitors having larger capacitance at high frequencies used for the electric equipment have been strongly demanded. To meet this demand, multilayer chip capacitors are suitable in terms of low ESR and multilayer solid electrolytic capacitors are suitable in terms of low ESR and large capacitance. However, in addition to lowering ESR by further increasing capacitance per volume, it has been desired that ESL due to external connection terminals of a capacitor be decreased further.
JP 2000-58376 A discloses a capacitor having a three-terminal structure, where a first anode terminal and a second anode terminal, which are connected to an anode, are provided on two opposed side surfaces of the capacitor, and a cathode terminal connected to a cathode is provided on another side so as to lower the ESL. JP 2001-155952 A discloses a capacitor having a three-terminal structure, where a first anode terminal and a second anode terminal, which are connected to an anode, are provided on a top surface of the capacitor and a cathode terminal connected to a cathode is provided on a bottom surface so as to lower the ESL and the ESR.
The following describes conventional multilayer capacitors, with reference to
FIGS. 8A and 8B
and
FIGS. 9A and 9B
.
FIG. 8A
is a perspective view showing the appearance of one example of the conventional multilayer capacitors, and
FIG. 8B
is a cross-sectional view of the capacitor.
As shown in
FIG. 8A
, on each of both opposed side surfaces of a ceramic dielectric block
31
, a first electrode terminal
32
or a second electrode terminal
33
is formed, and a third electrode terminal
34
is formed on a surface other than the above surfaces. As shown in
FIG. 8B
, inside of the ceramic dielectric block
31
, anodes
35
and cathodes
36
are laminated, between which a ceramic dielectric
37
intervenes. Edges of the anodes
35
on one side are connected collectively to the first electrode terminal
32
, and edges on the other side are connected collectively to the second electrode terminal
33
. The cathodes
36
are collected at a side that is not illustrated in the drawing and are connected to the third electrode terminal
34
.
Such a multilayer capacitor is connected to a circuit board by connecting a bottom surface
32
a
of the first electrode terminal
32
, a bottom surface
33
a
of the second electrode terminal
33
and a bottom surface
34
a
of the third electrode terminal
34
to the respective land patterns on the circuit board.
FIG. 9A
is a perspective view showing the appearance of another example of the conventional multilayer capacitors, and
FIG. 9B
is a perspective view showing a construction of electrodes of the capacitor. As shown in
FIG. 9A
, a first electrode terminal
39
and a second electrode terminal
40
are formed on a top surface of a ceramic dielectric block
38
, and a third electrode terminal
41
is formed on a bottom surface thereof. As shown in
FIG. 9B
, anodes
42
and cathodes
43
are laminated, between which a ceramic dielectric
44
intervenes. First and second anode leading-out portions
42
a
and
42
b
are formed on a top side of the anode
42
, and a bottom side of the cathode
43
is used for a cathode leading-out portion
43
a
. The first anode leading-out portion
42
a
, the second anode leading-out portion
42
b
and the cathode leading-out portion are connected to the first electrode terminal
39
, the second electrode terminal
40
and the third electrode terminal
41
, respectively.
The multilayer capacitor shown in
FIGS. 9A and 9B
is intended to be embedded in a multilayered print board formed by laminating a plurality of wiring layers. The first electrode terminal
39
and the second electrode terminal
40
are connected to a wiring conductor of upper wiring layers and the third electrode terminal
41
is connected to a wiring conductor of lower wiring layers.
As described above, conventionally, multilayer capacitors having three or more terminals are used for realizing low ESL and low ESR at high frequencies. In these capacitors, inductance is lowered by passing a current inside of a capacitor efficiently and by making an anode and a cathode function as a circuit wiring.
However, since all of the multilayer capacitors used at high frequencies have three or more terminals, their structure is complicated and a circuit wiring has to be designed depending on the number of terminals.
On the other hand, in order to lower the ESL with a two-terminal structure, efforts have been made only for reducing the size until now, and a multilayer capacitor that can realize low ESL and large capacitance at the same time has not been provided.
SUMMARY OF THE INVENTION
In the present invention, an anode and a cathode are led out in a same direction. According to one aspect of the present invention, a capacitor includes: anodes and cathodes that each are laminated alternately with at least a dielectric layer intervening therebetween; at least one anode leading-out portion; at least one cathode leading-out portion; an anode terminal; and a cathode terminal. The anodes are connected electrically to the at least one anode leading-out portion, and the cathodes are connected electrically to the at least one cathode leading-out portion. The at least one anode leading-out portion and the at least one cathode leading-out portion are led out in a predetermined direction. The at least one anode leading-out portion is connected to the anode terminal and the at least one cathode leading-out portion is connected to the cathode terminal.


REFERENCES:
patent: 5473503 (1995-12-01), Sakata et al.
patent: 5621608 (1997-04-01), Arai et al.
patent: 5930109 (1999-07-01), Fishler
patent: 6110234 (2000-08-01), Sakata et al.
patent: 6185091 (2001-02-01), Tanahashi et al.
patent: 6224639 (2001-05-01), Hamada et al.
patent: 6262878 (2001-07-01), Shirashige et al.
patent: 1 050 888 (2000-11-01), None
patent: 61-183524 (1986-11-01), None
patent: 6-267802 (1994-09-01), None
patent: 7-201671 (1995-08-01), None
patent: 9-129512 (1997-05-01), None
patent: 2765462 (1998-04-01), None
patent: 11-288846 (1999-10-01), None
patent: 2000-058376 (2000-02-01), None
patent: 2000-215729 (2000-08-01), None
patent: 2001-006978 (2001-01-01), None
patent: 2001-155952 (2001-06-01), None

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