Capacitively coupled references for isolated...

Details Capacitively coupled references for isolated... Capacitively coupled references for isolated...

2001-04-16

2002-09-03

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S120000

Reexamination Certificate

active

06445330

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to isolation method for analog-to-digital converter systems, and more particularly a method and apparatus for isolating an ADC using a capacitive isolation system.
BACKGROUND OF THE INVENTION
FIG. 1
is a block diagram of a measurement system
9
of the Prior Art. Such measurement systems may be used to measure various analog parameters in environments where voltage isolation is required. For example, in power monitoring systems (e.g., residential power metering) a measurement device (front end) may be measuring power at line voltage (e.g.,220 Volts) and some form of isolation may be required to protect the user and processor (back end) which may be at a much lower potential. Similarly, in medical systems, voltage isolation may be required as a fail-safe to prevent a patient from being electrocuted due to potential differences between various medical monitoring devices.
Referring to
FIG. 1
, measurement system
9
may include a digital signal processor (DSP)
11
, link chip
12
, capacitor C
1
13
, analog-to-digital converter (ADC) and link chip
15
, and a sensor
16
. Sensor
16
may comprise any one of a number of known analog sensors for measuring a particular parameter (e.g., temperature, pressure, voltage, amperage, power consumption, or the like).
Analog-to-digital converter (ADC) and link chip
15
may convert the analog output of sensor
16
to a digital value (typically a one-bit data stream) and outputs this data stream to a digital signal processor (DSP)
11
via link chip
12
and isolation capacitor
13
. In addition to digital data values transmitted from analog-to-digital converter (ADC) and link chip
15
to digital signal processor (DSP)
11
, other signals may need to be exchanged between the two chips.
For example, clock signals and control signals (including calibration signals or voltage levels) may be transmitted from digital signal processor (DSP)
11
to analog-to-digital converter (ADC) through link chip
15
. In addition, digital signal processor (DSP)
11
may need to provide power supply voltage to analog-to-digital converter through link chip
15
. In the Prior Art, additional signal lines may be required for such additional signals, increasing the complexity and cost of the device.
As noted above, in many applications, such as power metering, it may be necessary to isolate analog-to-digital converter (ADC) from link chip
15
and digital signal processor (DSP)
11
due to differences in voltage potential. To isolate the voltage potential between analog-to-digital converter and link chip
15
and digital signal processor (DSP)
11
, an isolation capacitor
13
may be employed.
Such isolation practices, however, may create problems when attempting to communicate from digital signal processor (DSP)
11
and link chip
15
an analog-to-digital converter (ADC) and vice versa. With a small capacitance value C
1
for capacitor
13
, the use of a digital tri-state gate in link chip
12
and link chip portion of analog-to-digital converter (ADC) and link chip
15
for transmitting data is disadvantageous due to voltage division losses. Nevertheless, using a digital tri-state gate is advantageous for transmitter energy, clock, and command sources, as well as for receiver systems. However, when a transmitter produces a square wave according to a Manchester encoded clock and control scheme, for example, isolation capacitor
13
may block the square wave from the transmitting transformer.
FIG. 2
is a block diagram of another embodiment of a measurement system
19
of the Prior Art. Measurement system
19
includes a digital application specific integrated circuit (ASIC) or programmable logic device (PLD)
21
such as a digital signal processor and link chip, a resistor
22
, capacitor
23
, transformer
24
, analog-to-digital converter (ADC)
25
and capacitor
26
.
ASIC or PLD
21
may include a transmitter
27
and receiver
29
coupled to each other through switch
28
. Data may be selectively transmitted and received over the connection between ASIC or PLD
21
and ADC
25
. In addition, ASIC or PLD
21
may provide power to ADC
25
through this same link.
ADC
25
may include a diode
30
and a rectifier
31
. Signals from secondary winding
33
of transformer
24
may be rectified by rectifier
31
and diode
30
to produce a voltage a capacitor
26
which in turn is the power supply for ADC
25
.
As in the embodiment of
FIG. 1
, transmitter
27
may transmit to primary winding
32
of transformer
24
a square wave which may be partially blocked or distorted by capacitor
23
from transformer
24
. ADC
25
may detect a pause during the tri-state operation and takes over the data link, sending data and status back to receiver
29
. During this take-over period, however, voltage at power supply
26
may droop significantly if many bits are transmitted, and full logic levels may not re-establish themselves.
In addition, an isolated ADC may require an accurate low noise reference voltage from, for example, a microcontroller. If the ADC is rendered in CMOS, a superquality voltage reference may be required for the ADC to accurately measure analog values. CMOS circuitry may be more susceptible to drift due to temperature variations and the like, as well as initial accuracy of measurement.
Further, in order to perform an absolute accurate conversion with an isolated ADC, it may be necessary to send an accurate low noise reference voltage across the isolation barrier. If the ADC is rendered in CMOS, a superquality voltage reference may be required for the ADC to accurately measure analog values. CMOS circuitry may be more susceptible to drift due to temperature variations and the like, as well as initial accuracy of measurement. A better reference, therefore, may be implemented on the isolated side.
Moreover, in some applications, it may be necessary to provide multiple isolated ADCs with precision matched gains for acquiring related signals such that conversion data are known to be exactly at the same scale. These may be ratiometric measurements between several isolated points. Prior art techniques may use separate chips for each ADC side to provide a reference signal. However, such a solution creates extra cost and increases complexity and size of the overall circuitry.
SUMMARY OF THE INVENTION
The present invention provides an alternative to Prior Art isolation techniques by providing a capacitively coupled reference voltage and a capacitively coupled gain calibration. The isolation technique of the present invention is based upon the idea of a capacitive divider. In a preferred embodiment, the capacitive divider may comprise a near unity gain capacitive divider.
If the load or parasitic capacitance is Cload and the isolation capacitance is Ciso, then the gain between input and output can be calculated as:
Vout/vin=
(
Ciso
)/(
Ciso+Cload
)
which will be nearly unity (i.e., 1) when Ciso>>Cload. In addition, if Ciso>>Cload, the gain will also be largely insensitive to variations in Ciso and Cload. For example, if Cin is 100 ppm of Ciso, then a 10% variation in Ciso or Cload results in only a 10 ppm variation in the voltage gain.
In an alternative embodiment, Ciso could be well matched to Cload to create a capacitive voltage divider. However, in such an embodiment, the isolation capacitance Ciso should be matched to load capacitance Cload with fluctuations in temperature and other conditions.


REFERENCES:
patent: 5016014 (1991-05-01), Bitting
patent: 5030954 (1991-07-01), Ribner
patent: 6087970 (2000-07-01), Panicacci
patent: 6104794 (2000-08-01), Hein et al.
patent: 6208685 (2001-03-01), Yamazaki
patent: 6262921 (2001-07-01), Manning
patent: 6288661 (2001-09-01), Holberg

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