Active solid-state devices (e.g. – transistors – solid-state diode – Alignment marks
Reexamination Certificate
2000-12-15
2003-02-11
Potter, Roy (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Alignment marks
C257S528000, C257S532000
Reexamination Certificate
active
06518679
ABSTRACT:
FIELD OF INVENTION
The present invention relates generally to the field of microelectronics manufacturing and, more particularly, to a structure and method for precisely aligning a first circuit image region of a microelectronic chip with a second circuit image region of a wafer.
BACKGROUND OF THE INVENTION
A continuing need exists for joining microelectronic chips to one another. For example, in the field of application specific integrated circuits (ASICs) it is often desirable to join memory chips, such as DRAM, NVRAM and FeRAM, to logic chips. The greatest opportunity for allowing the maximum number of interface connections between two chips is to join the chips face-to-face. In this manner, the circuit image regions of the two chip are directly exposed to each other over the largest possible surface area. In addition, joining chips face-to-face minimizes the distance and material required to make the interconnections as well as minimizes electrical interference between the conductors used to make the interconnections.
Joining chips face-to-face, however, requires precise alignment between the corresponding circuit image regions. Presently, the tolerance for alignment is on the order of about 100-150 nm, and this tolerance will only decrease as circuit features become smaller as time progresses. Optical registration tools, such as an “M” tool developed for integrated circuit fabrication, are suitable for face-to-face alignment of microelectronic chips but are only capable of crude alignment. The “M” tool comprises a prism that allows a tool operator to simultaneously view registration marks on the adjacent faces of two chips as the faces are brought proximate one another. The prism, however, must be located between the two chips for the operator to observe the opposing registration marks. When the chips are spaced from one another by a distance slightly larger than the height of prism, the prism must be removed before the chips can be moved closer together. The height of the prism is enormous by modem lithographic standards. After the tool operator removes the prism, optical observation of the opposing surfaces is no longer possible and the tool operator must close the gap without any information concerning the alignment or non-alignment of the registration marks. Even under the best conditions, misregistration would greatly exceed the fine tolerances allowable by the present invention.
U.S. Pat. No. 5,130,660 to Flint et al. shows a miniature electronic device aligner for precisely aligning an optical device, such as a laser, with a package substrate. The package substrate includes a detector plate and two energized capacitor plates actively energized by sinusoidal signals 180 degrees out of phase with one another. The optical device includes a passive capacitor plate that, when the optical plate is properly aligned with the package, extends over the two capacitor plates and the detector plate on the package. The actively energized capacitor plates passively drive the passive capacitor plate. When the optical device is properly aligned, the out-of-phase charges induced by the energized capacitor plates cancel each other in the passively driven plate and the signal sensed by the detector plate is at a minimum.
The Flint et al. aligner is not capable of the fine resolution necessary to align two bodies to a tolerance of on the order of 150 nm or less, which is required for joining two microelectronic chips to one another. In addition, the Flint et al. aligner cannot provide different levels of resolution for aligning two bodies with one another when the bodies are spaced from each other by different distances. Moreover, the Flint et al. aligner cannot sense the tilt of one body with respect to another body. The present invention overcomes these and other limitations of conventional micro-alignment structures and methods.
SUMMARY OF THE INVENTION
In one aspect, the present invention is directed to a structure for aligning a first body and a second body relative to one another. The structure includes a plurality of passive coupling elements attached to the first body and spaced from one another. The structure further includes a plurality of first driven electrodes attached to the second body and spaced from one another. A plurality of second driven electrodes are attached to the second body and are spaced from and located alternatingly with the plurality of first driven electrodes. A plurality of sensing electrodes are attached to the second body and are spaced from and located alternatingly with the plurality of first driven electrodes and the plurality of second driven electrodes.
In another aspect, the present invention is directed to a method of aligning a first body and a second body with one another, wherein one of the first and second bodies has a plurality of electrodes arranged in a first set, a second set and a third set. Each set comprises at least two electrodes. The electrode in the first, second and third sets are located alternatingly with one another. The method includes driving the at least two electrodes in the first set with a first varying electrical signal and driving the at least two electrodes in the second set with a second varying electrical signal that is out of phase with said first varying electrical signal. Then, at least one of said first and second bodies is moved such that at least one of said passive coupling element is proximate at least two of the plurality of electrodes. A third electrical signal from at least one of the electrodes in the third set is sensed.
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Lu Ning
Pricer Wilbur David
Whiting Charles Arthur
Downs Rachlin & Martin PLLC
Potter Roy
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