Coded data generation or conversion – Analog to or from digital conversion – Digital to analog conversion
Reexamination Certificate
2000-12-01
2002-06-04
JeanPierre, Peguy (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Digital to analog conversion
C341S144000, C341S172000
Reexamination Certificate
active
06400299
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a digital/analog (D/A) converter using capacitors.
2. Description of the Related Art
In order to decrease the occupied area while the resolution is high, capacitance type D/A converters have been developed.
A first prior art D/A converter is constructed by capacitors having binary weighted capacitance that are connected to an output terminal. Also, analog switches are provided that are controlled by input digital data connected to the capacitors. Each of the analog switches applies a low reference voltage or a high reference voltage to the corresponding capacitor in accordance with the corresponding input digital data. Thus, the first prior art D/A converter can generate an analog voltage in accordance with the input digital data (see JP-A-63-67920). This will be explained later in detail.
In the above-mentioned first prior art D/A converter, however, since the total capacitance of the capacitors is still large. Thus, the occupied area is still large.
In second and third prior art D/A converters, in order to more decrease the total capacitance, coupling capacitors are added to the first prior art D/A converters (see JP-A-57-124933 & JP-A-4-72819). This also will be explained later in detail.
In the above-mentioned second and third prior art D/A converters, however, the total capacitance is still large, which would increase the occupied area.
SUMMARY OF THE INVENTION
It is object of the present invention to provide a capacitance type D/A converter capable of further decreasing the total capacitance.
According to the present invention, in a D/A converter for converting 2n-bit input digital data into an analog output voltage where n is 2, 3, . . . , 2n capacitors, (n−1) coupling capacitors and 2n analog switches are provided. If k is 1, 2, . . . , n, a (2k−1)-th capacitor has a unit capacitance, and a 2k-th capacitor has a capacitance twice the unit capacitance. A first terminal of the (2k−1)-th capacitor is connected to a first terminal of the 2k-th capacitor. Also, if m is 1, 2, . . . , n−1, an m-th coupling capacitor is connected between the first terminal of the 2m-th capacitor and the first terminal of the (2m+1)-th capacitor, while an (n−1)-th coupling capacitor is connected to the output terminal. If m′ is 2, 3, . . . , n−1, the first coupling capacitor has the unit capacitance, and an m′-th one of coupling capacitors has a capacitance of the unit capacitance plus a quarter of the capacitance of an (m′−1)-th coupling capacitor. Each of the analog switches is responsive to one of the 2n input digital data and is connected between a second terminal of one of the capacitors and two power supply sources.
Note that, if the 2n-th capacitor and the 2n-th analog switch are omitted, the D/A converter serves as a (2n−1)-bit D/A converter.
REFERENCES:
patent: 4404544 (1983-09-01), Dwaraknath
patent: 4843393 (1989-06-01), Kuraishi
patent: 4937578 (1990-06-01), Shioda
patent: 5235335 (1993-08-01), Hester et al.
patent: 5274376 (1993-12-01), Phillips et al.
patent: 5889486 (1999-03-01), Opris et al.
patent: 57-124933 (1982-08-01), None
patent: 63-67920 (1988-03-01), None
patent: 4-72819 (1992-03-01), None
Jean-Pierre Peguy
JeanGlaude Jean Burner
NEC Corporation
Young & Thompson
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