Capacitance reduction by tunnel formation for use with a...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Junction field effect transistor

Reexamination Certificate

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C257S522000, C257S758000, C257S774000

Reexamination Certificate

active

06909128

ABSTRACT:
A method used during the manufacture of a semiconductor device comprises providing at least first, second, and third spaced conductive structures, where the second conductive structure is interposed between the first and third conductive structures. A first dielectric is formed over these conductive structures, then a portion of the first dielectric layer is removed which forms a hole in the dielectric layer to expose the second conductive structure. Subsequently, the second conductive structure is removed to leave a void or tunnel in the dielectric layer where the second conductive structure had previously existed. Finally, a second dielectric layer is provided to fill the hole but to leave the void or tunnel in the dielectric layer subsequent to the formation of the second dielectric layer. An inventive structure resulting from the inventive method is also described.

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patent: 6451669 (2002-09-01), Torres et al.
patent: 6589861 (2003-07-01), Park et al.

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