Capacitance multiplier circuit exhibiting improving bandwidth

Details Capacitance multiplier circuit exhibiting improving bandwidth Capacitance multiplier circuit exhibiting improving bandwidth

2006-09-26

2006-09-26

Barnie, Rexford (Department: 2819)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

C327S541000, C330S085000, C330S260000

Reexamination Certificate

active

07113020

ABSTRACT:
A monolithic capacitance multiplication circuit serves to reduce the required die area when larger capacitance values are needed such as in filter and loop frequency compensation circuits. A current mirror/cascoding device arrangement reduces the effective series resistance of the multiplier capacitor. As a result, the multiplier topology exhibits improved bandwidth over prior art capacitance multiplier circuits.

REFERENCES:
patent: 5900771 (1999-05-01), Bremner
patent: 6084475 (2000-07-01), Rincon-Mora
patent: 6633193 (2003-10-01), Halamik et al.
patent: 6812778 (2004-11-01), Yeo et al.
patent: 2003/0071675 (2003-04-01), Stair et al.

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