Capacitance multiplier circuit

Details Capacitance multiplier circuit Capacitance multiplier circuit

2006-12-29

2008-12-16

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S552000, C327S558000, C327S524000

Reexamination Certificate

active

07466175

ABSTRACT:
An integrated circuit including a capacitance multiplier having reduced parasitics and injected noise compared to conventional multiplier methods. The integrated circuit includes a reference capacitor and a current mirror arrangement coupled to the reference capacitor. The current mirror arrangement, which includes a current gain factor N, varies the capacitance of the reference capacitor by a factor of N+1, based on the reference capacitor current. The current mirror arrangement includes an operational amplifier operating in conjunction with two mirror transistors to form a current mirror arrangement having little or no series resistance. The current mirror also can include a plurality of resistors configured to reduce the noise from the capacitance multiplier, thus making the capacitance multiplier useful for applications that may require relatively low noise.

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G. A. Rincon-mora, “Active Capacitor Multiplier in Miller-Compensated Circuits,” IEEE J. Solid State Circuits, vol. 35, No. 1, pp. 26-32, Jan. 2000

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