Capacitance multiplier circuit

Details Capacitance multiplier circuit Capacitance multiplier circuit

1981-07-23

1987-11-24

Clawson, Jr., Joseph E.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307297, 3072992, 528127, 528128, 357 36, 357 51, 357 81, H03K 402

Patent

active

047091592

ABSTRACT:
A capacitance multiplier circuit is disclosed which is fabricated using integrated circuit techniques comprising an inverted multiple collector transistor structure wherein a first one of the multiple collectors is electrically shorted to the base of the transistor to form a current mirror. The collector areas between the first collector and a second one of the multiple collectors are area ratioed to provide a multiplication factor, which is determined by the ratio between the areas of the two collector regions. The capacitance value formed between the junction of the base and the second collector regions is multiplied by this multiplication factor to produce an effective capacitance at the second collector. The multiplication factor is independent to process and temperature variations.

REFERENCES:
patent: 3633052 (1972-01-01), Hanna
patent: 3911296 (1975-10-01), Davis
patent: 4081822 (1978-03-01), Oao et al.

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