Capacitance measurement method

Details Capacitance measurement method Capacitance measurement method

2002-11-05

2004-05-18

Le, N. (Department: 2858)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

For fault location

C324S658000

Reexamination Certificate

active

06737870

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a capacitance measurement method using a CBCM (Charge Based Capacitance Measurement) circuit.
2. Description of the Background Art
(Basic Principle of CBCM Technique)
A CBCM technique is a method for measuring capacitance values on a sub-fF level (≦10
−15
F) that cannot be measured with sufficient accuracy by AC measurement equipment such as an LCR meter.
FIG. 7
is a circuit diagram illustrating a configuration of a CBCM circuit adopting a conventional CBCM technique. As shown, a PMOS transistor MP
1
and an NMOS transistor MN
1
are connected in series, and a PMOS transistor MP
2
and an NMOS transistor MN
2
are connected in series. The source of the PMOS transistor MP
1
is connected to a power pad
52
, the source of the PMOS transistor MP
2
is connected to a power pad
54
, and the sources of the NMOS transistors MN
1
and MN
2
are connected in common to ground level. A PMOS gate potential Gp is applied to the gates of the PMOS transistors MP
1
and MP
2
, while an NMOS gate potential Gn is applied to the gates of the NMOS transistors MN
1
and MN
2
.
A reference capacitance C
ref
(reference value=C
m
(dummy capacitance)) is provided between drain (node N
1
) and source of the NMOS transistor MN
1
, and a test capacitance C
tst
(capacitance value=C
m
+C
t
(target capacitance)) is provided between drain (node N
2
) and source of the NMOS transistor MN
2
. The purpose of the CBCM circuit shown in
FIG. 7
is to measure the target capacitance C
t
.
FIG. 8
is a timing chart illustrating the operation of the CBCM circuit shown in FIG.
7
. Hereinbelow, with reference to this drawing, capacitance measurement by the conventional CBCM circuit will be described.
As shown, input voltage waveforms of the PMOS gate potential Gp and the NMOS gate potential Gn are such that at least either the NMOS transistors MN
1
, MN
2
or the PMOS transistors MP
1
, MP
2
are in the off state at any given time. Thus, no short circuit current flows from the PMOS transistor MP
1
to the NMOS transistor MN
1
or from the PMOS transistor MP
2
to the NMOS transistor MN
2
.
As shown in
FIG. 8
, during a time interval between t
1
and t
2
, the PMOS transistors MP
1
and MP
2
are turned on to supply currents I
r
and I
t
from the power pads
52
and
54
and thereby to charge the reference capacitance C
ref
and the test capacitance C
tst
. During this time, the NMOS transistors MN
1
and MN
2
are both in the off state and thus, potentials at the nodes N
1
and N
2
which are connected respectively to the reference capacitance C
ref
and the test capacitance C
tst
reach a power supply potential V
dd
.
During a time interval between t
2
and t
3
, the PMOS transistors MP
1
, MP
2
and the NMOS transistors MN
1
, MN
2
are all in the off state. Ideally, the accumulated charges on the reference capacitance C
ref
and the test capacitance C
tst
should be stored and the nodes N
1
and N
2
should be maintained at the power supply potential V
dd
.
During a time interval between t
3
and t
4
, only the NMOS transistors MN
1
and MN
2
are in the on state. Thus, the accumulated charges on the reference capacitance C
ref
and the test capacitance C
tst
are discharged to ground level and the potentials at the nodes N
1
and N
2
reach a ground potential V
ss
.
During a time interval between t
4
and t
5
, all the MOS transistors are in the off state. Ideally, the reference capacitance C
ref
and the test capacitance C
tst
should be maintained at the ground potential V
ss
since the completion of discharge.
These are one cycle T of operation (the time from t
1
to t
5
) and hereinafter, this operation will be repeated. To be observed by the measurement equipment is average values of the currents I
r
and I
t
with respect to time. Where f(=1/T) is the frequency of the gate input waveforms (Gp, Gn), the target capacitance value C
t
can be obtained from the following equations (1) and (2).
I
C
=I
t
−I
r
  (1)
C
t
=
C
tst
-
C
m
=
I
C
V
dd
·
f
(
2
)
The advantage of the CBCM technique is that, as expressed in Equations (1) and (2), the dummy capacitance (parasitic capacitance) C
m
can be cancelled and a desired target capacitance C
t
can be obtained.
In this way, the CBCM technique allows measurement of capacitance values. In the capacitance measurement technique using the CBCM circuit, however, if there is leakage of charge from the test resistance C
tst
and the amount of leakage cannot be ignored as compared with the amount of charging current (e.g., 1% or more as a current value), treating the observed current I
t
as a charging current will cause an error of the measured capacitance value.
FIG. 9
is a circuit diagram showing an equivalent circuit on the side of the test capacitance C
tst
, where there is no leakage current. As shown, if there is no leakage current, the circuit configuration is equivalent to that in which the test capacitance C
tst
and a resistance R
s
(such as a transistor's resistance) are connected in series.
FIG. 10
is a circuit diagram showing an equivalent circuit on the side of the test capacitance C
tst
, where there is a leakage current. As shown, if there is a leakage current, the circuit configuration is such that a resistance R
t
is additionally connected parallel to the test capacitance C
tst
.
FIG. 11
is a circuit diagram showing an equivalent circuit of the CBCM circuit when there is a leakage current. As shown, the circuit configuration shown in
FIG. 10
is connected between drain and source of the NMOS transistor MN
2
, and the current I
t
supplied from the power pad
54
flows as a current IC
t
through the test capacitance C
tst
and flows as a current IR
t
through the resistance R
t
.
FIG. 12
is an explanatory diagram for indicating a problem of the leakage current. As shown, even during the period in which the PMOS transistor MP
1
is in the on state with the application of the PMOS gate potential Gp (i.e., during the period in which the NMOS transistor MN
1
should be in the off state), the current IR
t
will flow as a leakage current.
Capacitance measurement (extraction) using the conventional CBCM technique assumes that currents observed on the side of power supply potential V
dd
are all used for charging the MOS transistors forming the CBCM circuit, the test capacitance C
tst
, and the dummy capacitance C
m
. Thus, if there is a leakage current, even a charge which actually corresponds to a leakage current flowing through the resistance R
t
is treated as an accumulated charge, which causes a problem that the measured capacitance value may become larger than the actual capacitance value.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a capacitance measurement method which is capable of measuring an accurate capacitance value even if a leakage current on a level that cannot be ignored occurs in a capacitance to be measured.
According to the present invention, the capacitance measurement method is for measuring a capacitance to be measured which is connected to a CBCM (Charge Based Capacitance Measurement) circuit including a charge transistor, and includes the following steps (a) to (e). The step (a) is to apply to the charge transistor a first control signal for controlling turning on/off of the charge transistor in a predetermined cycle, thereby to measure an amount of first test current to be supplied through the charge transistor to the capacitance to be measured. The step (b) is to apply to the charge transistor a second control signal for controlling turning on/off of the charge transistor in the predetermined cycle, thereby to measure an amount of second test current to be supplied through the charge transistor to the capacitance to be measured. A period during which the second control signal indicates an on state of the charge transistor is set to be predetermined times longer than that during which the first control signal indicates an on state of th

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