Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
2001-10-16
2003-03-18
Pham, Long (Department: 2823)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
C438S239000, C438S254000, C438S255000, C438S393000, C438S397000, C438S398000, C438S399000
Reexamination Certificate
active
06534377
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a capacitance element and a method of manufacturing the same, and more particularly, to a concave type capacitance element and a method of manufacturing the same.
FIG. 7
is a cross sectional view of a conventional concave type capacitance element, which is denoted generally at
500
.
FIGS. 8A-8C
is a cross sectional view of manufacturing steps of the capacitance element
500
. The capacitance element
500
will now be described with reference to
FIGS. 8A-8C
.
Among the manufacturing steps of the conventional capacitance element
500
, first, as shown in
FIG. 8A
, insulation regions
52
and active regions
53
sandwiched by the insulation regions
52
are formed on the surface of silicon substrate
51
. Following this, silicon oxide layers
54
are formed so as to cover the surface of the silicon substrate
51
. Aperture portions (not shown) are formed in the silicon oxide layers
54
, and polycrystalline silicon is buried in the aperture portions so that plugs
55
are formed. Further, a silicon nitride film
56
and a silicon oxide layer
57
are deposited.
Next, as shown in
FIG. 8B
, the silicon oxide layer
57
and the silicon nitride film
56
are etched into an approximately cylindrical shape using a photoresist (not shown) as a mask, whereby aperture portions
60
are formed. Following this, a storage node (SN) layer
61
of polycrystalline silicon doped with phosphorus, for instance, is formed so as to cover the entire surface. The storage node layer
61
is electrically connected with the active regions
53
of the silicon substrate
51
through the plugs
55
.
Next, as shown in
FIG. 8C
, a photoresist (not shown) is formed inside the aperture portions
60
, and the storage node layer
61
is etched so that the storage node layer
61
remains only within the aperture portions
60
. This allows an isolation wall
65
to isolate the storage node layers
61
of adjacent capacitors from each other.
Following this, a capacitor isolation film
62
of silicon nitride, for example, and a cell plate layer
64
of polycrystalline silicon, for example, are formed successively.
Through these steps described above, the capacitance element
500
as that shown in
FIG. 7
is completed in which the adjacent capacitors are isolated from each other by the isolation wall
65
.
During the manufacturing steps of the capacitance element
500
, isolation between the storage node layers
61
of the adjacent capacitors is insufficient and an inconvenience therefore occurs that the capacitors short-circuit with each other. For instance, as shown in
FIG. 9
, when a foreign matter
63
adheres onto the storage node layers
61
on the isolation wall
65
, the storage node layers
61
fail to be isolated from each other. However, it is possible to find such an inconvenience through an electric inspection (wafer test) on the capacitance element
500
after the manufacturing steps.
However, there is a situation as that shown in
FIG. 8C
that the adjacent storage node layers
61
short-circuit with each other as a conductive foreign matter
63
in an etching solution adheres onto the isolation wall
65
during etching of the storage node layers
61
. In such a situation, since the short-circuit of the adjacent storage node layers
61
is on a smaller scale as compared with such an inconvenience as that shown in
FIG. 9
, it is more difficult to find the inconvenience by the wafer test and eliminate the inconvenience in advance.
As a result, the capacitance element
500
with such an inconvenience is used as it is directly as a product, which causes a failure in the market.
SUMMARY OF THE INVENTION
Noting this, the present invention aims at providing a capacitance element which prevents short-circuit induced by an adhering conductive foreign matter between adjacent storage node layers.
More particularly, the present invention is directed to manufacturing method of a capacitance element in which a plurality of aperture portions are formed in an insulation layer on a semiconductor substrate and a storage node layer is formed in the inner surfaces of the aperture portions, comprising: a step to form an insulation layer on a semiconductor substrate; a step to form a silicon oxide film on the insulation layer; a step to form a plurality of aperture portions in the insulation layer from the surface of the silicon oxide film; a step to form a conductive layer so as to cover the insulation layer and the silicon oxide film; a step to remove the conductive layer on the silicon oxide film so that the conductive layer remaining inside the aperture portions becomes storage node layers; a silicon oxide film removing step to remove the silicon oxide film; and a step to successively form a capacitor insulation film and a cell plate layer so as to cover the storage node layers.
Using this manufacturing method, it is possible to remove a conductive foreign matter together with the silicon oxide film, and therefore, prevent short-circuit induced by an adhering conductive foreign matter between the adjacent storage node layers.
Further, the present invention is directed to a manufacturing method, further comprising a step to form a silicon nitride film between the insulation layer and the silicon oxide film, wherein the silicon oxide film removing step is a step to etch back the silicon oxide film using the silicon nitride film as an etching stopper.
This is because it is possible to selectively remove the silicon oxide film by means of this step.
Further, the present invention is directed to a manufacturing method wherein the insulation layer is formed by a CVD silicon oxide layer formed by a CVD method while the silicon oxide film is formed by a coated silicon oxide film formed by a coating method, and the silicon oxide film removing step is a step to selectively etch the coated silicon oxide film using a hydrofluoric acid solution.
This is because it is possible to selectively remove the silicon oxide film by means of this step.
It is preferable that the CVD silicon oxide layer is formed by one layer selected between a BPSG layer and a TEOS layer, and the coated silicon oxide layer is formed by a SOG film.
Meanwhile, the present invention is directed also to a manufacturing method of a capacitance element in which a plurality of aperture portions are formed in an insulation layer on a semiconductor substrate and a storage node layer is formed at inner surfaces of the aperture portions, comprising: a step to form an insulation layer on a semiconductor substrate; a step to form a silicon nitride film on the insulation layer; a step to form a plurality of aperture portions in the insulation layer from the surface of the silicon nitride film; a step to selectively etch the insulation layer at side walls of the aperture portions while coating the surface of the insulation layer with the silicon nitride film so that the silicon nitride film projects like a hood from the top surface of the insulation layer; a step to form a conductive layer so as to cover the insulation layer and the silicon nitride film; a step to remove the conductive layer on the top surface and side surfaces of the silicon nitride film so that the conductive layer remaining inside the aperture portions becomes storage node layers; and a step to successively form a capacitor insulation film and a cell plate layer so as to cover the storage node layers.
The silicon nitride film is formed on the storage node layers in the manufacturing method, and therefore, it is possible to prevent short-circuit between the adjacent storage node layers.
It is preferable that the insulation layer is formed by a silicon oxide layer, and the selective etching step is a step to selectively etch, with a hydrofluoric acid solution, the silicon oxide film at the side walls of the aperture portions using the silicon nitride film as an etching mask.
The present invention is further directed to a capacitance element comprising a plurality of storage node layers insulated from each other, characterized in compris
Mitsubishi Denki & Kabushiki Kaisha
Pham Long
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