Capacitance element

Details Capacitance element Capacitance element

2002-10-24

2003-06-03

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Passive components in ics

C257S535000, C257S528000, C257S371000, C257S372000, C257S386000, C257S401000

Reexamination Certificate

active

06573588

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a capacitance element in a semiconductor integrated circuit, and more particularly relates to a capacitor structure in CMOS processes.
2. Description of the Prior Art
FIG. 7
is a schematic sectional view showing a capacitance element of a conventional example 1. Referring to the figure, reference numeral
1
denotes a p type semiconductor substrate;
2
denotes a buried N well region (also referred to as a bottom N well);
3
denotes a P well region;
4
denotes a n+ active region in which the concentration of an type impurity is high;
5
denotes an insulation film such as an oxide film;
6
denotes a gate electrode formed of polysilicon or the like;
7
denotes a n+ active region;
8
denotes a p+ active region;
9
denotes another n+ active region;
10
denotes another p+ active region; and
12
denotes a N well region that electrically leads out the buried N well region
2
to the upper portion. Here, “n+” and “p+” represent that the concentrations of a n type impurity and a p type impurity are high, respectively.
In addition, reference symbol A
1
represents a lead wire from the n+ active region
9
, and the lead wire A
1
is connected with a power supply Vdd. A
2
represents a lead wire from the n+ active region
7
; A
3
represents a lead wire from the gate electrode
6
; A
4
represents a lead wire from the p+ active region
8
; and A
5
represents a lead wire from the other p+ active region
10
. The lead wire A
5
is connected with the ground GND.
Further, reference symbol T
1
represents one terminal that is formed by electrically connecting the lead wire A
2
and the n+ active region
7
, and T
2
represents the other terminal that is formed by electrically connecting the lead wire A
3
and the gate electrode
6
. T
3
and T
5
each represent a ground terminal connected with the ground GND, and T
4
represents a power supply terminal connected with the power supply Vdd. Additionally, C
1
represents a capacitance formed between the gate electrode and the n+ active region
4
that was formed by means of n+ implantation (the high-concentration implantation of an n-type impurity or dopant), and C
2
represents capacitance formed between the buried N well region
2
and the P well region located on the N well region
2
.
FIG. 8
is a CV curve showing the voltage dependence of a capacitance value in the capacitance element of the conventional example 1, and the horizontal axis shows the potential of the terminal T
2
to the terminal T
1
. As is apparent from the CV curve, the capacitance value reduces as the potential reduces from the vicinity of 0 V toward the inversion side, and shows the curve that projects downward. Such voltage dependence becomes a problem when building an analog circuit.
An example of a circuit in which the voltage dependence of the capacitance causes the accuracy deterioration of the circuit will now be shown as below.
FIG. 9
is a sample holding (S/H) circuit having the simplest configuration. Referring to the figure, the circuit is composed of a switch TG and a holding capacitor CH. Vin represents an input terminal, and Vout represents an output terminal.
The operation will next be described below.
The output signal of this sample holding circuit is received by a buffer amplifier (not shown) usually having extremely high input impedance, and is sent to the following step. The switch TG is turned on during a sampling period, and thereby the analog input voltage applied to the input terminal is applied to the capacitor CH. The switch TG is turned off during a holding period, and the charge having been accumulated in the capacitor CH for the sampling period is thereby maintained. The analog voltage on hold is then output through a buffer circuit AMP having a high input impedance.
FIG. 10
shows how such a sample holding circuit operates, by use of the operation waveforms. The vertical axis shows the voltage, and the horizontal axis shows the time. Referring to the figure, Vin shows the input voltage, Vout shows the output voltage at the normal operating time, and TG shows the clock wave. TG shows the sampling period (on) and the holding period (off).
The operation at that time will next be described in a little more detail. More specifically, for the “ON” period when the analog input is sampled into the holding capacitor, the input voltage Vin is divided by the on resistance Ztg of the switch TG and the impedance Zc formed by the capacitor CH, and thereby a voltage that is slightly different from the input voltage is applied to the capacitor CH. For the “OFF”(holding) period, the voltage having been applied to the capacitor CH for the sampling period is held, and the voltage is output as an averaged voltage.
As is apparent from the operation thereof, the voltage applied to the capacitor CH is distorted when the resistance of the switch TG or the capacitance of the capacitor CH has voltage dependence. The resistance of a switch usually has voltage dependence, but the influence thereof can be reduced by means of using a large switch. However, there is nothing to be done about the influence of the voltage dependence of the capacitor. It has been difficult to produce a sample holding circuit having a higher degree of accuracy than a certain level.
Referring to
FIG. 10
, Vout′ shows how the accuracy of the waveform is reduced by the voltage dependence. The actual distortion of the voltage cannot be shown in such a figure, but the distortion can be observed by means of highly accurate measurement. The figure is slightly exaggerated for purposes of illustration.
The capacitance element of a conventional example 2 will next be illustrated in FIG.
11
. Referring to the figure, reference numeral
1
denotes a p type semiconductor substrate;
2
denotes a buried N well region (bottom N well);
3
denotes a P well region;
5
denotes an insulation film such as an oxide film;
6
denotes a gate electrode formed of polysilicon or the like;
8
denotes a p+ active region;
9
denotes another n+ active region;
10
denotes a lead wire from another p+ active region
8
; and
12
denotes a N well region that electrically leads out the buried N well region
2
to the upper portion. Reference symbol A
1
represents a lead wire from the n+ active region
9
, and the lead wire A
1
is connected with a power supply Vdd. A
3
represents a lead wire from the gate electrode
6
; A
4
represents a lead wire from another p+ active region
8
; and A
5
represents a lead wire from the other p+ active region
10
, and is connected with the ground GND.
Further, reference symbol T
1
represents one terminal that is formed by electrically connecting the lead wire A
4
and the p+ active region
8
, and T
2
represents the other terminal that is formed by electrically connecting the lead wire A
3
and the gate electrode
6
. T
3
represents a power supply terminal, and T
5
represents a ground terminal. Additionally, C
1
represents capacitance formed between the gate electrode
6
and the p well region
3
.
FIG. 12
is a CV curve showing the voltage dependence of a capacitance value in the capacitance element of the conventional example 2, and the horizontal axis shows the potential of the terminal T
2
to the terminal T
1
. As is apparent from the figure, the voltage dependence appears from the vicinity of zero bias voltage also in the capacitance element of the conventional example 2 illustrated in
FIG. 11
similarly to the conventional example 1 illustrated in FIG.
7
. Therefore, the accuracy of the circuit is reduced by the voltage dependence of the capacitance also in this capacitance element.
In the conventional example 1 illustrated in
FIG. 7
, the increase of the impurity concentration in the n+ region can reduce the voltage dependence of the capacitance element. However, the voltage dependence thereof slightly remains even if the method is used. In this respect, the

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