Image analysis – Applications – Personnel identification
Reexamination Certificate
1999-11-12
2004-01-20
Werner, Brian (Department: 2621)
Image analysis
Applications
Personnel identification
C382S108000
Reexamination Certificate
active
06681033
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a capacitance detecting apparatus and its inspecting method as well as a fingerprint checking apparatus, particularly to a capacitance detecting apparatus preferably used as a fingerprint detecting apparatus and its inspecting method as well as a fingerprint checking apparatus using the detecting apparatus.
2. Description of Related Art
As a fingerprint detecting apparatus, there has been known a method in which detection electrodes are arranged in an array on a surface of a semiconductor and as shown by
FIG. 17
, when a finger is put on an overcoat
102
covering the detection electrodes
101
, capacitances Cs formed in accordance with recesses and projections of a fingerprint between the detection electrodes
101
and a surface of the finger, are detected to thereby sample a pattern of a fingerprint (fingerprint pattern) (for example, refer to U.S. Pat. No. 5,325,442).
According to the capacitance Cs formed between the detection electrode
101
and the surface of the finger, a capacitance value is increased at a portion of a ridge or the fingerprint since a distance between the ridge portion and the detection electrode
101
is shortened, the capacitance is reduced at a portion of a valley of the fingerprint since a distance between the ridge portion and the detection electrode
101
is lengthened and accordingly, the pattern of the finger print can be sampled by detecting the capacitance Cs. As a method of detecting the capacitance Cs, there are conceivable two methods of a current charge method and a voltage charge method.
The former current charge method is a method in which after flowing constant current Ic during a constant time period of Tc from the detection electrode
101
, that is, after charging constant electric charge &Dgr;Q to the detection electrode
101
, a voltage change &Dgr;V of the detection electrode
101
is detected. The voltage change &Dgr;V and the capacitance Cs are in an inversely proportional relationship as is apparent: from the following equation (1).
&Dgr;
V=&Dgr;Q/Cs=IcTc/Cs
(1)
The latter voltage charge method is a method in which after charging electric charge to the detection electrode
101
by constant voltage &Dgr;Vc, the electric charge &Dgr;Q is detected. The electric charge &Dgr;Q and the capacitance Cs are in a proportional relationship as is apparent from the following equation (2).
&Dgr;Q=Cs&Dgr;Vc
(2)
FIG. 18
shows a circuit constitution of a conventional example of a fingerprint detecting apparatus using the current charge method. In the drawing, row drive lines
111
and column sense lines
112
are wired in a matrix shape in respect of the detection electrodes
101
arranged in an array. An NchMOS transistor Q
1
of a source follower and an NchMOS transistor Q
2
for selecting a row are connected in series between a power source line
113
and the column sense line
112
. Further, the gate of the MOS transistor Q
1
is connected to the detection electrode
101
and the gate of the MOS transistor Q
2
is connected to the row drive line
111
, respectively.
Further, a PchMOS transistor Q
3
and a charge current source Ic are connected in series between the power source line
113
and the ground. Further, the gate of the MOS transistor Q
3
is connected to a reset line
114
. Further, a common connection point P for connecting the MOS transistor Q
3
and the charge current source Ic is connected to the detection electrode
101
via an NchMOS transistor Q
4
. Further, the gate of the MOS transistor Q
4
is connected to a charge control line
115
.
The circuit having the above-described constitution is provided to each of the detection electrodes
101
, that is, the unit cell. Here, an explanation will be given of operation of the circuit in reference to timing charts of FIG.
19
.
First, the MOS transistor Q
2
is brought into an ON state by being applied with a row drive signal RAD at a high level (hereinafter, described as “H” level) via the row drive line
111
and successively, the MOS transistor Q
4
is brought into an ON state by being applied with a charge control signal CEN at “H” level via the charge control line
115
. Thereby, selection of row is carried out.
Simultaneously with the row selection, the MOS transistor Q
3
is brought into an ON state by being applied with a reset signal XRST of a low level (hereinafter, described as “L” level) via the reset control line
114
. Thereby, voltage (hereinafter, referred to as detection voltage) Vs of the detection electrode
101
is reset to power source voltage VDD which is reference voltage. Thereafter, by transition of the reset signal XRST to “H” level, the MOS transistor “Q
3
” is brought into an OFF state. Thereby, electric charge produced by the current source Ic starts charging to the detection electrode
101
via the MOS transistor Q
4
.
After elapse of the constant time period Tc, the charge control signal CEN transits to “L” level by which the MOS transistor Q
4
is brought into an OFF state. Thereby, the electric charge finishes charging to the detection electrode
101
. A change amount V at this occasion from resetting the detection voltage Vs is given by Equation (1). The detection voltage Vs is read by the row column sense line
112
via the MOS transistor Q
1
of the source follower and the NchMOS transistor Q
2
for selecting the row and is outputted to outside via the column sense line
112
.
As described above, according to the conventional fingerprint checking apparatus using the current charge method, by detecting the voltage Vs of the detection electrode
101
produced by charging the constant electric charge &Dgr;Q, the capacitance Cs formed between the detection electrode
101
and the surface of the finger can be detected. However, the detection voltage Vs is constituted to output via a plurality of transistors or in the case of this example, via the MOS transistors Q
1
and Q
2
and accordingly, there poses a problem in which S/N of the detection signal is deteriorated by a dispersion in characteristics of these transistors such as a threshold value Vth or ON resistance in respective cells.
Further, in order to efficiently sense the detection voltage Vs of the respective detection electrode
101
, there are needed a plurality of the charge current sources Ic having the same current value (in the case of this example, the charge current sources Ic are prepared for the respective cells) and therefore, a dispersion in current values of these current sources Ic constitute one factor of deteriorating S/N.
Further, the voltage Vs must be sampled while maintaining the electric charge of the detection electrode
101
and accordingly, a source follower circuit (in the case of this example, MOS transistor Q
1
) needs to use, the gate of the MOS transistor Q
1
is connected to the detection electrode
101
and accordingly, there is a concern of causing electrostatic breakdown at the gate portion when, for example, a charged finger is put thereon.
In the meantime, in the case of the voltage charge method, switching elements of a number of rows for selecting the rows are connected to respective column sense lines by a number of rows and accordingly, relative to the capacitance Cs to be sensed, parasitic capacitance Cs
1
p of the column sense line for sampling thereof is very large and therefore, in order to sample electric charge which is charged to the capacitance Cs, some devise is needed.
As an example, in the constitution shown by
FIG. 17
, when a size of the detection electrode
101
is set to 80 &mgr;m×80 &mgr;m, a material of the overcoat
102
is SiN and its thickness is set to 1.0 &mgr;m, assuming the specific inductive capacity of SiN as 7.5, a maximum value Cs (MAX) of the capacitance Cs becomes 425 (fF).
In contrast thereto, when a number of detection rows is set to 128, parasitic capacitance of the switching element to be connected is set to 5 (fF) and parasitic capacitance of wirings is set to 0.4 (pF/mm), the pa
Koyama Takeshi
Shinozaki Keiichi
Takeda Masashi
Yano Motoyasu
Kananen, Esq. Ronald P.
Miller Ryan J.
Rader & Fishman & Grauer, PLLC
Sony Corporation
Werner Brian
LandOfFree
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