Motion video signal processing for recording or reproducing – Local trick play processing – With randomly accessible medium
Reexamination Certificate
1998-04-28
2002-07-16
Christensen, Andrew B. (Department: 2615)
Motion video signal processing for recording or reproducing
Local trick play processing
With randomly accessible medium
C386S349000, C348S207110
Reexamination Certificate
active
06421496
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention concerns a signal processing circuit suitable to use for a camcorder.
2. Description of Related Art
In recent years, a camcorder capable of recording image signals picked-up by a image pick-up device or external input signals supplied from an external input terminal by a video tape recorder (VTR) or playing back video signals recorded by VTR has been popularized.
FIG. 4
shows an example of a block diagram for an existent signal processing circuit applied to the camcorder described above. A signal processing circuit shown in
FIG. 4
comprises, as main blocks, a CCD
11
(Charge Coupled Device) solid state image pick-up device (hereinafter referred to simply as “CCD”), an auto gain control circuit
13
(hereinafter referred to as “AGC circuit”), an A/D converter
14
, an on-screen display (OSD)
15
, a camera signal processing block
20
, a timing generation block
30
, a burst lock block
40
, a line input comb filter block
50
, an external inputting phase locked loop (hereinafter referred to as “PLL”) circuit block
60
and the like.
The CCD
11
is adapted to optoelectronically convert an image coupled by way of a not-illustrated optical lens to an image pick-up device and output the same as image signal.
The AGC circuit
13
is adapted to conduct gain control for the image signal supplied from the CCD
11
to a switch
12
upon camera photographing or a VTR reproduced video signal supplied by way of the switch
12
upon VTR playing back.
The A/D converter
14
is adapted to convert analog image/video signals gain controlled in the AGC circuit
13
. into digital image/video signals.
The on-screen display
15
serves as display control section for display of character information or the like on a monitor such as a view finder.
The camera video signal processing block
20
is constituted, for example, with an LSI (Large Scale Integration) in which a signal processing circuit
21
, D/A converters
22
a
,
22
b
are disposed as a signal processing circuit system, and frequency dividers
24
-
27
, a phase comparator
28
and a switch
29
are disposed as a clock processing circuit system.
The signal processing circuit
21
comprises various kinds of circuits for applying predetermined processing when the image signal is supplied from the CCD
11
and a YC separation comb filter for removing cross talks and noises when the reproduced video signal is supplied from the VTR (hereinafter referred to as “reproduced type filter”).
The D/A converter
22
a
converts a digital luminance signal (Y signal) outputted from the signal processing circuit
21
into a analog luminance signal, while the A/D converter a
22
b
converts digital color (chroma) signal (C signal) outputted from the signal processing circuit
21
into an analog chromatic signal.
The timing generation block
30
controls driving timing of the CCD
11
in which a CCD driving timing generation circuit
31
and a frequency divider
32
are provided. The timing generation block
30
is also constituted with an LSI.
The burst block
40
forms a signal in synchronization with a burst signal contained in a line input signal inputted from a line input terminal T
41
, in which are provided a switch
41
a sync separation circuit
42
, a color aburst separation circuit
43
, a phase comparator
44
and a frequency divider
45
. The burst lock block
40
is also constituted with an LSI.
The line input comb filter block
50
conducts YC separation processing for a line input signal inputted from the line input terminal T
41
, in which a YC separation comb filter (hereinafter referred to as “line comb filter”)
51
for conducting YC separation of the line input signal. The line input comb filter block
50
is also constituted with an LSI or the like.
The external input PLL circuit block
60
forms and supplies a clock CK, a horizontal sync signal HD and a vertical sync signal VD in synchronization with the external input signal to the on-screen display
15
when the external input signal such as the line input signal or the VTR reproduced video signal, in which a horizontal/vertical sync separation circuit
61
, a phase comparator
62
, a frequency divider
63
, a voltage controlled oscillator (VCO)
64
and a low pass filter (LPF)
65
are provided.
The operation of the signal processing circuit
100
described above will be explained.
At first, explanation is to be made for the operation during camera recording for recording the image signal picked-up by the CCD
11
in the VTR.
Upon camera recording, the switch
12
and the switch
29
of the camera signal processing block
20
are controlled so as to be in contact with contacts t
1
as shown in FIG.
4
. In this case, the image signal picked-up by the CCD
11
is supplied by way of the switch
12
, the AGC circuit
13
, and the A/D converter
14
to the signal processing circuit
21
of the camera signal processing block
20
and applied with a predetermined processing by the signal processing circuit
21
. Then, they are put to D/A conversion by the D/A converters
22
a
,
22
b
and outputted as a luminance signal Y
1
and a chromatic signal C
1
from terminals T
22
, T
23
respectively and are supplied, for example, to a display circuit block or a VTR signal processing block in the succeeding stage not illustrated.
As the clock forming processing during camera recording, a clock 4Fsc four times as high as a sub-carrier signal Fsc (14.3 MHz where the television system is NTSC system, or at 17.3 MHz when the television system is PAL system), and the clock 4Fsc is used as a standard clock for operating the camcorder.
The standard clock 4Fsc is supplied to the frequency divider
24
and the frequency divider
25
.
The frequency divider
24
divides the standard clock 4Fsc into 1/4, which is supplied from a terminal T
25
as a sub-carrier signal Fsc. The sub-carrier signal Fsc is supplied to a not-illustrated VTR signal processing block as a modifying signal upon recording the image picked-up by the CCD
11
in VTR.
The frequency divider
25
divides the standard clock 4Fsc by a predetermined dividing ratio (for example 1/910 in a case of NTSC system and 1/1135 in a case of PAL system) and outputs the same, for example, as a horizontal sync signal to one terminal (+) of a phase comparator
28
.
An output from the frequency divider
26
is supplied to the other terminal (−) of the phase comparator
28
, and the phase comparator
28
outputs a result of phase comparison between the output from the frequency divider
25
and the output from the frequency divider
26
.
The output from the phase comparator
28
is inputted by way of a terminal T
24
to the low pass filter (LPF)
16
and supplied by way of the LPF
16
to the voltage control oscillator (VCO)
17
. Therefore, the VCO
17
is controlled for the oscillation frequency by the output of the phase comparator
28
. The output from the VCO
17
is supplied by. way of a terminal T
31
to the frequency divider
32
of the timing generation block
30
. The frequency divider
32
divides the output from the VCO
17
into 1/2, and the divided output is supplied as a master clock MCK from a terminal T
32
by way of a terminal T
28
of the camera signal processing block
20
to the frequency divider
26
. The frequency divider
26
divides the master clock MCK by a divisional ratio 1/FH and outputs the same to the other terminal (−) of the phase comparator
28
. The dividing ratio 1/FH of the frequency divider
26
is determined by the number of pixels of the CCD
11
.
They constitute a PLL circuit for controlling the oscillation frequency of the VCO
17
, and in a state in which the PLL circuit is locked, the master clock MCK is synchronized with the standard clock 4Fsc outputted from the crystal oscillator
23
.
The master clock MCK is supplied to the CCD driving timing generation circuit
31
of the timing generation block
30
, the on-screen display
15
and by way of the switch
29
of the camera signal processing block
20
to the signal
Chieu Po-lin
Christensen Andrew B.
Kananen Ronald P.
Rader & Fishman & Grauer, PLLC
Sony Corporation
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