CAM/RAM memory device with a scalable structure

Details CAM/RAM memory device with a scalable structure CAM/RAM memory device with a scalable structure

2000-05-19

2001-12-11

Mai, Son (Department: 2818)

Static information storage and retrieval

Associative memories

Ferroelectric cell

C365S189070, C365S230030

Reexamination Certificate

active

06330177

ABSTRACT:

FIELD OF INVENTION
The present invention relates to a CAM/RAM memory device with a scalable and flexible structure. CAM/RAM in this document means that the memory device functions both as a CAM (Content Addressable Memory) with matching operations and also has all ordinary RAM (Random Access Memory) functionality, i.e. a memory device with a CAM match operation mode and a RAM addressed read mode, where selectable parts of the memory cells can be masked off for the CAM mode and reading and writing may be performed directly through an address decoder in the RAM addressed read mode. CAM/RAM memory devices are especially useful, but not limited to, address look-up devices. The memory device employs a block structure for an efficient use of the silicon area. Blocks are arranged in parallel with common word lines running through all the blocks and operative in both RAM read/write and CAM look-up. By means of the present invention the word lines may be blocked between parallel blocks allowing a valid CAM match read out from more than one block simultaneously.
STATE OF THE ART
CAM memories are attractive for use in address look-up devices, and there are many different implementations of doing so. A general structure contains a CAM memory where selectable parts can be masked off to implement different look-up schemes and get the ability to handle hierarchical addresses. To get an efficient handling of address learning and changes of the look-up table it is also desirable to have a CAM that in parts works as an ordinary RAM. For address flexibility it is also desirable to have the partitions into CAM and pure RAM configurable. There exists a number of different ways of achieving these memories and examples include those described in e.g. U.S. Pat. No. 5,383,146 (Threewitt) and U.S. Pat. No. 5,706,224 (Srinvasan et al.).
When using the above mentioned CAM/RAM devices, some new problems arise. For reasons of simplicity and size it is desirable to use the same word line when reading data generated by a CAM match, as in the case of an ordinary RAM addressed read, i.e., the match function should activate the same word lines as the address decoder. The priority function handling CAM matches takes care of ensuring that only one match is generated in a block of memory. Hits in different blocks should be prioritised by logic outside the memory block controlling the multiplexer used by RAM reads as well. This creates a problem when a multiple match generates hits on different positions of the blocks as shown in
FIG. 2
b
described more in detail below. Here it is obvious that two word lines are activated simultaneously, which causes invalid data from all memory blocks. One way to avoid this would be to have a separate address decoder for each block of memory, but, as stated before, since simplicity and size is important, this is not a satisfying alternative.
The present invention solves this problem by placing a blocking means between the memory blocks as shown in
FIG. 2
c,
thereby enabling a selection of whether or not to propagate the word line. This creates a way of isolating the word line for each memory block in the case of a matching operation, and of keeping the shared word line for ordinary RAM addressed reads and writes. The area for this block of propagation gates is small compared to the demand of seperate address decoders for each block.
SUMMARY OF THE INVENTION
The present invention provides a CAM/RAM memory device with a scalable structure comprising a memory divided into blocks. Each block has a number of rows of memory cells. An address decoder is connected by word lines to the cells in a row of the blocks and a multiplexer is adapted to select which block of memory to read data from. Vertical match data lines implement the CAM functionality of the memory device.
According to the invention the memory device includes means for blocking the word lines between the blocks. Particularly, the blocking means is adapted to block the word lines when the memory device is in a CAM match read mode, such that several parallel hits in different blocks may be used for CAM match operations, without generating an invalid read-out. The memory device has a very useful application as a device for handling address look-up, e.g. in a switch or router.
The scope of the invention is defined in the accompanying claims.
By means of his arrangement, the invention makes efficient use of the available silicon area. Also, the memory device is flexible since all the memory cells may be handled directly in RAM mode for reading and writing. Thus, the data structure is easily changed including the mask data of the CAM functionality.


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