Static information storage and retrieval – Associative memories – Ferroelectric cell
Reexamination Certificate
2002-06-06
2004-06-22
Auduong, Gene (Department: 2818)
Static information storage and retrieval
Associative memories
Ferroelectric cell
C365S149000, C365S227000
Reexamination Certificate
active
06754093
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated content addressable memory (CAM) arrays, and in particular to low-power CAM arrays.
DISCUSSION OF RELATED ART
Conventional random access memory (RAM) arrays include RAM cells (e.g., static RAM (SRAM) cells, dynamic RAM (DRAM) cells, and non-volatile RAM (NVRAM) cells) that are arranged in rows and columns, and addressing circuitry that accesses a selected row of RAM cells using address data corresponding to the physical address of the RAM cells within the RAM array. A data word is typically written into a RAM array by applying physical address signals to the RAM array input terminals to access a particular group of RAM cells, and applying data word signals to the RAM array input terminals that are written into the accessed group of RAM cells. During a subsequent read operation, the physical address of the group of RAM cells is applied to the RAM array input terminals, causing the RAM array to output the data word stored therein. Groups of data words are typically written to or read from the RAM array one word at a time. Therefore, a relatively small portion of the entire RAM array circuitry is activated at one time to perform each data word read/write operation, so a relatively small amount of switching noise occurs within the RAM array, and the amount of power required to operate the RAM array is relatively small.
In contrast to RAM arrays, content addressable memory (CAM) arrays store data values that are accessed in response to their content, rather than by a physical address. Specifically, during compare (search) operations, a CAM array receives a searched-for data value that is simultaneously compared with all of the data words stored in the CAM array. In response to each searched-for data value applied to the CAM array input terminals, the rows of CAM cells within the CAM array assert or de-assert associated match signals indicating whether or not one or more data values stored in the CAM cell rows match the applied data value. Therefore, large amounts of data can be searched simultaneously, so CAM arrays are often much faster than RAM arrays in performing certain functions, such as search engines.
While CAM arrays are faster than RAM arrays in performing search functions, they consume significantly more power and generate significantly more switching noise than RAM arrays. In particular, in contrast to RAM arrays in which only a small portion of the total circuitry is accessed during each read and write operation, significantly more power is needed (and noise is generated) in a CAM array because, during compare (search) operations, all of the CAM cells are accessed simultaneously, and those CAM cells that do not match the applied search data value typically switch an associated match line from a high voltage to a low voltage. Switching the large number of match lines at one time consumes a significant amount of power.
To reduce the total power consumed by CAM arrays, there is a trend toward producing CAM arrays that operate on low system (operating) voltages. To facilitate lower system voltages, the integrated circuit (IC) fabrication technologies selected to produce such CAM arrays utilize smaller and smaller feature sizes. In general, the smaller the feature size of an IC, the lower the operating voltage that is used to operate the IC. However, when IC feature sizes and operating voltages are reduced too much, the amount of charge stored at each node within the CAM array becomes so small that a “soft error” problem arises, which is discussed below with reference to FIG.
1
.
FIG. 1
is a simplified cross sectional view showing an exemplary IC feature (e.g., a drain junction utilized to form an n-type transistor) that comprises an n-type diffusion (node)
50
formed in p-type well (P-WELL)
51
, which in turn is formed in a p-type substrate
52
. Dashed line capacitor
53
represents the capacitance of node
50
, and indicates that node
50
stores a positive charge.
As indicated in
FIG. 1
, if an energetic particle, such as an alpha particle (&agr;), from the environment or surrounding structure strikes the n-type diffusion of node
50
, then electrons (e) and holes (h) will be generated within the underlying body of semiconductor material (i.e., in p-well
51
or p-type substrate
52
). These free electrons and holes travel to the node
50
and p-well
51
/p-substrate
52
, respectively, thereby creating a short circuit current that reduces the charge stored at node
50
. If the energy of the alpha particle is sufficiently strong, or if the capacitance
53
is too small, then node
50
can be effectively discharged. When node
50
forms a drain in an SRAM cell and the charge perturbation is sufficiently large, the stored logic state of the SRAM cell may be reversed (e.g., the SRAM cell can be flipped from storing a logic “1” to a logic “0”). This radiation-produced data change is commonly referred to as a “soft error” because the error is not due to a hardware defect and the cell will operate normally thereafter (although it may contain erroneous data until rewritten).
Many approaches have been proposed for dealing with soft errors, such as increased cell capacitance or operating voltage, and error detection schemes (such as using one or more parity bits). While these proposed approaches are suitable for standard RAM arrays, they are less desirable in CAM arrays. As pointed out above, CAM arrays inherently consume more power than RAM arrays. Therefore, while increased cell size and/or operating voltage can be tolerated in a RAM array, such solutions are less desirable in a CAM arrays. Moreover, adding error detection schemes to CAM arrays increase the size (and, hence, the cost) of the CAM arrays, and further increase power consumption.
Accordingly, what is needed is a CAM circuit that addresses the soft error problem associated with the low power CAM operating environment without greatly increasing the cost and power consumption of the CAM circuit.
SUMMARY
The present invention is directed to a CAM circuit that addresses the soft error problem associated with the low power CAM operating environment by providing a doped layer below both the logic and memory portions of each CAM cell that attracts electrons/holes generated by high energy particles (e.g., alpha particles), thereby reducing the chance of “soft error” discharge without greatly increasing the cost and power consumption of the CAM circuit.
In accordance with a first embodiment of the present invention, each CAM cell of the CAM circuit includes an SRAM cell and a comparator (logic) circuit, wherein both the SRAM cell and the comparator circuit are formed using at least one n-channel transistor having an n-doped storage region (junction node) formed in a p-type well, which in turn is formed in a p-type substrate. In this first embodiment, an n-type doped region is formed between the p-type well and the p-type substrate (i.e., below the n-doped storage regions of each n-channel transistor). Because the n-type doped layer is formed using a dopant having an opposite conductivity type than that of the well region and substrate, the n-type doped layer attracts electrons generated on either side of its boundary by energetic particles passing through the substrate. Accordingly, fewer electrons gather into the n-doped storage regions forming the transistor junctions of the SRAM cell and comparator circuit of each CAM cell. As a result, each CAM cell has a greater resistance to data corruption than that of conventional CAM structures, thereby facilitating the fabrication of CAM arrays having low operating voltages.
In accordance with a second embodiment of the present invention, the SRAM cell and comparator circuit of each CAM cell are formed using at least one p-channel transistor having an p-doped storage region formed in an n-type well, which in turn is formed in an n-type substrate. In this second embodiment, a p-type doped region is formed between the n-type well and the n-type substrate.
In accordance with a third embodiment of the present inv
Auduong Gene
Bever Hoffman & Harms LLP
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