Static information storage and retrieval – Associative memories – Ferroelectric cell
Reexamination Certificate
2002-07-24
2004-06-01
Elms, Richard (Department: 2824)
Static information storage and retrieval
Associative memories
Ferroelectric cell
C365S207000, C365S210130
Reexamination Certificate
active
06744653
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to semiconductor circuits, and more specifically to CAM cells and high speed and low power sense circuits for content addressable memory.
A content addressable memory (CAM) is a memory having an array of memory cells that can be commanded to compare all or a subset of the “entries” in the array against an input address. Each entry in the CAM array corresponds to the content of the cells in a particular row of the array. Each row of the array is further associated with a respective match line, which is used as a status line for the row. All or a portion of the CAM array may be compared in parallel to determine whether or not the input address matches any of the entries in the portion selected for comparison. If there is a match to an entry, then the match line for the corresponding row is asserted to indicate the match. Otherwise, the match line is de-asserted to indicate a mismatch (which may also be referred to as a “miss”). Typically, any number of match lines may be asserted, depending on the entries in the array and the input address.
In a typical CAM design, the comparison between a bit of the input address and the content of a CAM cell is performed by a comparison circuit included in the cell. The comparison circuits for all cells in each row may then be coupled to the match line for the row. For simplicity, the comparison circuits may be designed such that a wired-OR operation is implemented for the outputs from all comparison circuits coupled to any given match line. In one common design, the output for each comparison circuit is formed by the drain of an N-channel output transistor. This output transistor is turned ON if there is a mismatch between the input address bit and the memory cell content and is turned OFF otherwise. The match line may be pre-charged to a logic high prior to each comparison operation, and would thereafter remains at logic high only if all output transistors for the row are turned OFF, which would be the case if there is a match between all bits of the entry for the row and the input address. Otherwise, if at least one output transistor is turned ON due to a mismatch, then the match line would be pulled low by these transistors. The signal (or voltage) on the match line may thereafter be sensed or detected to determine whether or not there was a match for that row.
The conventional CAM cell and CAM sensing mechanism described above, though simple in design, have several drawbacks that affect performance. First, speed may be limited by the wired-OR design of the match line, if some speed-enhancing techniques are not employed. Each row may include a large number of cells (e.g., possibly 100 or more cells). In this case, if only one bit in the entire row does not match, then only one output transistor will be turned ON and this transistor will need to pull the entire match line low (e.g., from V
DD
to V
SS
). A long time (i.e., t=C·V
DD
2
/I, where C is the capacitance of each entire match line and I is the current of each transistor) may then be required to discharge the line, which would then limit the speed at which the CAM array may be operated. Second, excessive power may be consumed by the CAM design described above. Typically, only one row will match the input address, and all other rows will not match. In this case, all but one match line will be pulled to logic low (e.g., to V
SS
) by the output transistors that are turned ON due to mismatches. The power consumed may then be computed as (M−1)·C·V
DD
2
, where (M−1) is the number of mismatched rows, C is the capacitance of each match line, and V
DD
is the voltage swing of the match line during discharge.
As can be seen, there is a need for CAM cells and sense circuits that can ameliorate the shortcomings related to speed and power in the conventional design.
SUMMARY OF THE INVENTION
The invention provides CAM cell designs having improved performance over a conventional design. The invention further provides techniques to detect the signal (or voltage) on a match line coupled to a number of CAM cells and having faster speed of operation and possibly lower power consumption.
In an aspect, a content addressable memory (CAM) cell is provided having improved performance. The CAM cell includes a memory cell operable to store a bit value and a comparison circuit configured to detect the bit value stored in the memory cell. The comparison circuit includes (1) an output transistor coupled to a match line and configured to provide a drive for the match line based on the detected bit value, and (2) a dummy transistor coupled to a dummy line. The match line and dummy line are used to detect an output value provided by the CAM cell. In an embodiment, the dummy transistor (1) has similar dimension as the output transistor, (2) is located in close proximity to the output transistor, and (3) is turned OFF during sensing operation. The dummy transistor is used to achieve low voltage swing (small signal) sensing and provides for low power and high-speed operation.
In another aspect, a sense circuit is provided for sensing a logic state of a match line in a content addressable memory (CAM). The sense circuit includes a pair of amplifiers cross-coupled in a positive feedback configuration. The first amplifier has one input operatively coupled to the match line, and the second amplifier has one input operative to receive a reference signal. The match line is driven by a number of output transistors for a row of CAM cells. The reference signal is generated based on a row of dummy transistors that are similarly arranged as the output transistors. When enabled, the amplifiers detect the difference between the signals on the match line and the reference signal and further amplify the detected difference such that the logic value on the match line may be ascertained. The sense circuit may further include (1) a pair of pass transistors operatively coupled to the pair of amplifiers and used to enable the sense circuit, and (2) a switch coupled between outputs/inputs of the cross-coupled amplifiers and used to reset the amplifiers prior to each match line sense cycle. In a specific implementation, the first and second amplifiers may each be implemented as an inverter with gain (e.g., a P-channel transistor coupled in series with an N-channel transistor).
The match line is coupled to the output transistors for the row of CAM cells and may further be coupled directly to one input of the first amplifier. The dummy transistors couple to a dummy line that may further be coupled directly to one input of the second amplifier. Alternatively, the output transistors may also couple to a first common line that is coupled to the input of the first amplifier. In this case, the dummy transistors would similarly couple to a second common line that is coupled to the input of the second amplifier.
Various other aspects, embodiments, and features of the invention are also provided, as described in further detail below.
The foregoing, together with other aspects of this invention, will become more apparent when referring to the following specification, claims, and accompanying drawings.
REFERENCES:
patent: 5162681 (1992-11-01), Lee
patent: 5446686 (1995-08-01), Bosnyak et al.
patent: 5598115 (1997-01-01), Holst
patent: 6195277 (2001-02-01), Sywyk et al.
patent: 6307798 (2001-10-01), Ahmed et al.
patent: 6442054 (2002-08-01), Evans et al.
Dinh & Associates
Elms Richard
Hur J. H.
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