CAM cell with interdigitated search and bit lines

Details CAM cell with interdigitated search and bit lines CAM cell with interdigitated search and bit lines

2002-11-22

2004-07-06

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Associative memories

Ferroelectric cell

C365S189070, C365S063000

Reexamination Certificate

active

06760240

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to an integrated circuit content addressable memory (CAM) cells in which the search line and the bit line are interdigitated.
2. Description of the Related Art
Content addressable memory (CAM) cells are very popular for use in integrated circuits because of their flexibility, cost effectiveness, and other efficiency reasons. However, CAM cells have some inefficiencies relating to capacitance and capacitive coupling. The invention described below overcomes these problems by providing new structures that reduce capacitive coupling without requiring shielding or other complicated schemes.
BRIEF SUMMARY OF THE INVENTION
The invention discloses an array of content addressable memory (CAM) cells. Each of the CAM cells has a search line and a bitline parallel to the search line. Across the array, search lines and bit lines of the CAM cells are interdigitated so that the search lines and bitlines alternate across the array.
In the invention, a top matchline and bottom matchline run perpendicular to the search line and the bitline. The array includes macros that have at least two of the CAM cells. Within each of the macros one of the following structures exists: a bit line is between two search lines; or a search line is between two bit lines. Each of the macros includes a common match clock line shared by the CAM cells within each macro. The layouts of adjacent macros are inverted with respect to one another. Each of the macros have a top wordline and a bottom wordline. The top wordline and the bottom wordline cross between each of the CAM macros. A match clock signal runs through each of the macros. The match clock signal includes a jog to accommodate the inverted layout of the adjacent macros.
The invention also discloses a memory array that has a plurality of content addressable memory (CAM) macros. Each of the macros includes at least two CAM cells. The layouts of the macros are alternatively inverted with respect to one another within the array so that layouts of each macro are inverted with respect to adjacent macros and to balance parasitic capacitance across the array.
The invention reduces cross-coupling noise between signals in a CAM design by interdigitating search and bit lines. Since bit lines and search lines are never active at the same time, the invention provides effective noise shielding during either a search or read/write operation. The inactive lines provide the necessary shielding between active lines. Further, the invention connects macros of CAM cells so as to balance parasitic capacitance between mirrored cells without impacting cell size by twisting match lines at separate metal levels or jogging the natty clock line connection between macros. By ‘flip-flopping’ macros, total parasitic capacitance mismatch between C
1
and C
2
of the overall design is balanced.


REFERENCES:
patent: 6320777 (2001-11-01), Lines et al.

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