Static information storage and retrieval – Associative memories – Ferroelectric cell
Reexamination Certificate
2002-06-05
2004-01-13
Mai, Son (Department: 2818)
Static information storage and retrieval
Associative memories
Ferroelectric cell
C365S156000, C365S189070
Reexamination Certificate
active
06678184
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to content addressable memory (CAM) cell. More specifically, this invention relates to the structures and methods for improving area utilization of semiconductor substrate in a CAM cell.
BACKGROUND OF THE INVENTION
In the communication industry, there is often a need for determining associative relationships between a first data element and a second data element. To meet this need, a Content Addressable Memory (CAM) is used to make a comparison of an input data value and a stored data value in the CAM cell. For example, the input data value could be a packet header containing the address of a computer in a network of computers. The stored data values could be all the addresses of the computers within the network. A CAM cell array contained within a network router would determine whether there is an association between the address in the packet header and the addresses of the computers in the network. In determining the association, a search and comparison method must be performed between the address in the packet header and all the addresses in the network. This search and comparison method is both time and resource intensive using a traditional solutions consisting of RAM, CPU and software algorithm. Further, with large input data words such as 32 and 64 bits, the search and comparison method using traditional solutions is less efficient than a CAM cell array. Content Addressable Memories provide a solution for fast search and compare operations.
Generally a CAM cell is composed of a first memory circuit, a second memory circuit and a compare circuit. A CAM array is composed of individual CAM cells. Each CAM cell receives one bit of the input data word. The bit is compared to the data stored in the first memory circuit of the CAM cell. The second memory circuit of the CAM cell stores an enable value. The enable value is used to enable or disable a CAM cell in the CAM array during data comparison which allows a portion of the input data word to be enabled for comparison and another portion to be disabled for comparison during the match phase of the sequence.
There is a desire to reduce the semiconductor substrate area used by the CAM cell in order to provide an increase in performance and achieve improved packing density. The reduction in substrate area is determined by the placement, organization, and interconnections of the transistors of the CAM cell.
BRIEF SUMMARY OF THE INVENTION
Accordingly, an embodiment of the present invention provides a CAM cell comprising a first memory circuit, second memory circuit and a compare circuit. The first memory circuit comprises a six-transistor SRAM cell. The second memory circuit comprises a six-transistor SRAM cell. Of course, the memory circuits can be any acceptable memory circuits including flip-flops, EEPROM memory cells, cross-coupled invertors, NOR gates, or any other acceptable memory circuit. The compare circuit is a six-transistor structure organized in two parallel stacks of three transistors in one embodiment. Alternatively, a compare circuit having a five-transistor structure may be utilized having two parallel stacks each containing two transistors and a common fifth transistor.
The first memory circuit is coupled to a first word line, to a first bit line and to a second bit line. The first memory circuit stores a data value for comparing to an input data bit. The first memory circuit provides signals data-true and data-false to the compare circuit where the data signals are compared to first and second input data signals cf and ct. The second memory circuit is connected to a second word line, to the first bit line and to the second bit line. The second memory circuit stores a mask data value. The second memory circuit provides signal mask-true to the compare circuit to enable or disable the compare circuit.
According to an embodiment of the present invention, the interconnections of the transistors of the first and second memory circuits to the transistors of the compare circuit are comprised of regions of conductive material.
According to a first embodiment, the conductive material is polysilicon. In alternative embodiments, the conductive material is a metal layer, and can be any acceptable metal including aluminum, copper, tungsten, titanium polysilicides, or various combinations or alloys thereof. Of course, the type of conductive used can be changed within a cell from poly to a metal by the appropriate contacts, vias, and interconnections to provide a conductive path from the memory circuits to the appropriate nodes in the compare circuit.
An embodiment of the present invention provides a method of operating a CAM cell comprising the steps of storing data in the CAM cell; applying a signal to an enable line of the device wherein the enable line is a shared-gate structure, and thereby enabling the device; applying an input data; comparing the input data to the first data; and outputting a status change on a match signal line.
An embodiment of the present invention provides a method of operating a CAM cell wherein the step of storing further comprises the step of storing data in a first memory circuit and an enable value in a second memory circuit. To store data in the first memory circuit, a value is applied to a first word line; the data to a first bit line; the data complement to a second bit line; then storing a data value in a first memory circuit. An enable value is stored in a second memory circuit in a similar manner and is used to set an enable or disable terminal in the compare circuit.
In an embodiment of the present invention, a content addressable memory is formed in an integrated circuit having improved semiconductor substrate area utilization.
An embodiment of the present invention provides an improvement to the area utilization of the integrated circuit by reducing the layout area of the CAM cell, thus reducing the cost of manufacture. The embodiments of the present invention are applicable to binary and ternary CAM cells as well as four state CAM cells.
An advantage of the invention is that the CAM cell is fast in determining a match or no match decision when given a large data input word.
An advantage of the invention is a CAM cell with an improved organization of transistors that reduces the substrate area of the CAM cell and array.
An advantage of the invention is a CAM cell with an improved interconnection of transistors that is a small size for the CAM cell and array.
REFERENCES:
patent: 6044005 (2000-03-01), Gibson et al.
patent: 6108227 (2000-08-01), Voelkel
patent: 6373739 (2002-04-01), Lien et al.
patent: 6421265 (2002-07-01), Lien et al.
Frey Christophe
LaLanne Frederic
Lysinger Mark A.
Carlson David V.
Jorgenson Lisa K.
Mai Son
STMicroelectronics Inc.
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