Cam array with minimum cell size

Details Cam array with minimum cell size Cam array with minimum cell size

2000-05-18

2001-07-03

Nelms, David (Department: 2818)

Static information storage and retrieval

Associative memories

Ferroelectric cell

C365S204000

Reexamination Certificate

active

06256216

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to content addressable memory (CAM) arrays. More specifically, the present invention relates to ternary CAM cells and methods for operating these cells in a CAM array.
DISCUSSION OF RELATED ART
Unlike conventional random access memory (RAM) arrays, CAM arrays include memory cells that are addressed in response to their content, rather than by a physical address within a RAM array. That is, data words stored in a RAM array are accessed by applying address signals to the RAM array input terminals. In response to each unique set of address signals, a RAM array outputs a data value that is read from a portion of the RAM array designated by the address. In contrast, a CAM array receives a data value that is compared with all of the data values stored in rows of the CAM array. In response to each unique data value applied to the CAM array input terminals, the rows of CAM cells within the CAM array assert or de-assert associated match signals indicating whether or not one or more data values stored in the CAM cell rows match the applied data value.
CAM arrays are useful in many applications, such as search engines. For example, assume an employee list is searched to identify all employees with the first name “John”. The first names are written into a CAM array such that they are stored in a predetermined order (e.g., according to employee number). The input data value (“John”) is then applied to the CAM input terminals. When one or more stored data values match the input data value, the match line coupled to the one or more matching rows of CAM cells generates a high output signal. By identifying which rows have associated high match lines, and comparing those row numbers with the employee number list, all employees named “John” are identified. In contrast, to search a RAM array containing the same employee list, a series of addresses must be applied to the RAM array so that each stored data value is read out and compared with the “John” data value. Because each RAM read operation takes one clock cycle, a relatively large amount of time is required to read and compare a particular data value with all data values stored in a RAM array.
There are two types of CAM cells typically used in CAM arrays: binary CAM cells and ternary CAM cells. Binary CAM cells store one of two bit values: a logic high value or a logic low value. When the logic value stored in the binary CAM cell matches an applied data value, then the match line coupled to the binary CAM cell is maintained at a logic high value (assuming all other CAM cells coupled to the CAM array row also match), thereby indicating that a match has occurred. In contrast, when the logic value stored in the binary CAM cell does not match an applied data value, then the match line coupled to the binary CAM cell is pulled down, thereby indicating that a match has not occurred. Ternary CAM cells can store any one of three values: a logic high, a logic low, or a “don't care” value. When storing logic high and logic low values, a ternary CAM cell operates like a binary CAM cell. In addition, a ternary CAM cell storing a don't care value will provide a match condition for any data bit value applied to that CAM cell. This “don't care” capability allows CAM arrays to indicate when a data value matches a selected group of ternary CAM cells in a row of the CAM array. For example, assume each row of a ternary CAM array has eight ternary CAM cells. Additionally assume that the first four ternary CAM cells of each row each store one of a logic high and a logic low value (for comparison to the first four bits of an input 8-bit data value) and the last four ternary CAM cells of each row store “don't care” values. Under these conditions, when an
8
-bit data value is applied to the ternary CAM array, a match occurs for each row of the CAM array in which the data values stored in the first four ternary CAM cells match the first four bits of the applied 8-bit data value.
FIG. 1
is a schematic diagram of a prior art non-volatile ternary CAM cell
100
as described in U.S. Pat. No. 5,051,948. CAM cell
100
includes the minimum number of elements (i.e., two) for a ternary CAM cell: non volatile (i.e., floating gate avalanche) transistors MF
1
-MF
2
. CAM cell
100
stores one of a logic high, a logic low, and a don't care value by selectively programming/erasing transistors MF
1
-MF
2
during a write operation. During subsequent read operations, a data value (and its inverse data value) is applied to bit line BL (and inverted bit line BL#). Depending upon the programmed/erased state of transistors MF
1
-MF
2
, the word/match line WL/ML is either maintained in a charged state (indicating a match) or discharged to ground (indicating a no-match) in response to the data bit applied to bit line BL.
A problem with prior art CAM cell
100
is that the direct coupling of the gate of transistors MF
1
-MF
2
to bit line BL and inverted bit line BL#, respectively, make it difficult to read from non-volatile transistors MF
1
-MF
2
. An array of CAM cells similar to CAM cell
100
share bit line BL and inverted bit line BL# in a column and share word line/match line WL/ML in columns. It is difficult to read this array because the gate of each transistor MF
1
in a column of CAM cells coupled to bit line BL affects the voltage on bit line BL. Thus, a logic high voltage on bit line BL turns on all transistors MF
1
having a low threshold voltage in the column. Similarly, the gate of each transistor MF
2
in each column of CAM cells coupled to inverted bit line BL# affects the voltage on BL#. Thus, a logic high voltage on inverted bit line BL# turns on all transistors MF
2
having a low threshold voltage in the column. As a result, it is difficult to isolate a particular CAM cell in a column of an array to read. It would therefore be desirable to have a ternary CAM cell that has a minimum number of transistors that may be easily read.
SUMMARY
Accordingly, the present invention provides a CAM array including non-volatile ternary CAM cells that use access transistors to easily read from the non-volatile transistors. These access transistors enable isolation of individual CAM cells in a column of an array during a read operation. As a result, the access transistors of the CAM cells in a column of an array uninvolved in the read operation are turned off, thereby isolating the CAM cell in the column to be read. Each ternary CAM cell includes a pair of storage elements that are used to store a data bit value and an access element that is used during CAM array operation. During a comparison operation, when the applied data value matches the stored value, the storage elements de-couple the match line from a discharging bit line (i.e., a high voltage on the match line remains high). Conversely, when the applied data value does not match the stored value, the storage elements couple the match line to a discharging bit line, thereby discharging the match line.
Voltage on the match line is sensed by a conventional voltage sensor. Therefore, a slight drop in the voltage of the match line will register as a no-match condition. By sensing the slight voltage changes on the match line, the match line does not need to be completely discharged to determine the match
o-match condition of a CAM cell. Therefore, the power and time required to recharge the slightly discharged match line is less than that required to recharge a fully discharged match line.
The present invention will be more fully understood in view of the following description and drawings.


REFERENCES:
patent: 4780845 (1988-10-01), Threewitt
patent: 5051948 (1991-09-01), Watabe et al.
patent: 5111427 (1992-05-01), Kobayashi et al.
patent: 5319589 (1994-06-01), Yamagata et al.
patent: 5642320 (1997-06-01), Jang
patent: 5936873 (1999-08-01), Kongetira
patent: 5949696 (1999-09-01), Treewitt
patent: 6108227 (2000-08-01), Voelkel

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