Coded data generation or conversion – Converter calibration or testing
Reexamination Certificate
2002-07-29
2003-09-30
Wamsley, Patrick (Department: 2819)
Coded data generation or conversion
Converter calibration or testing
C341S154000
Reexamination Certificate
active
06628216
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to calibration, and more particularly to calibration of a resistor ladder using parallel resistive correction based on voltage difference measurements.
DESCRIPTION OF RELATED ART
Many electronic functions employ a resistor ladder to provide a sequential series of reference voltages. The present disclosure, for example, describes an analog to digital converter (ADC) that employs a reference resistor ladder to provide reference voltages for purposes of comparison and digital conversion. The desired level of linearity, accuracy and resolution of the particular ADC described herein is relatively high and requires 14-bit resolution of the input signal. The level of accuracy necessary for the resistor ladder depends upon the intended use of the ladder within the ADC. The ADC described herein employs the reference resistor ladder at the front end during initial conversion that is used to maintain the accuracy throughout the conversion process. For example, a selected portion of the reference voltages are applied as first inputs to preamplifiers, where the second inputs of each preamplifier is the sampled analog signal. In this manner, it is desired that the reference resistor ladder maintain better than 15-bit accuracy. It is noted that the present invention is not limited to ADC applications but may be applied to any application in which a resistor ladder is employed and in which it is desired to maintain a requisite accuracy level.
The ADC is intended to be incorporated into a monolithic unit on one substrate of an integrated circuit (IC) or chip. The overall passive component match for most silicon process is 0.1% in accuracy. This translates into overall accuracy of approximately 10 bits. Only a slight improvement is possible by careful optimization and use of dummy components in the layout of the passives. Sometimes, statistical matching using arrays of passives can yield up to an order of magnitude improvement in the overall accuracy.
Correction and calibration techniques are known to improve the resolution, such as laser trimming or fuse blowing. Such post-processing techniques, however, must be performed on a part-by-part basis thereby unduly complicating and increasing cost of the manufacturing process. Also, such post-processing techniques operate under fixed conditions and do not correct for inaccuracies or changes due to temperature, aging and/or operating conditions. Digital calibration techniques are also known and usually operate to measure error at the backend and apply a correction factor. These calibration techniques are limited by quantization of the calibrator and usually limits the correction to one-half bit of resolution of the converter itself. Also, the calibration techniques are incorporated in silicon and thus subject to the same limitations of the target circuitry.
It is desired to provide calibration for a resistor ladder that is not limited by the underlying substrate, that does not interfere with or overly complicate the manufacturing process, and that corrects for any potential inaccuracies that may arise during normal operation.
SUMMARY OF THE INVENTION
A calibration system for a resistor ladder includes a resistor tree of calibration resistors, a measurement circuit, and control logic. The resistor tree includes a plurality of calibration resistor branches, where each branch includes one or more pairs of complementary programmable resistors coupled together at a common junction and coupled in parallel with ladder resistors requiring calibration. The measurement circuit measures a voltage difference between a selected portion of the resistor ladder associated with a complementary pair of programmable resistors. The control logic controls the measurement circuit to measure a voltage difference between each complementary pair of to programmable resistors and to adjust the relative resistance of each complementary pair of programmable resistors to achieve a more equal voltage if the voltage difference is greater than a predetermined magnitude.
The resistor tree may be configured as a binary tree in which each successive branch includes twice the number of programmable resistors as a prior branch. The control logic adjusts each complementary pair of programmable resistors by increasing resistance of a first by an adjust amount and by decreasing resistance of a second by the same adjust amount. Each programmable resistor may be configured as a binary weighted resistor subladder, where each binary weighted resistor subladder is programmed by a digital value. The control logic may adjust the relative resistance in any desired manner, such as by incrementing a first digital value by one least significant bit and by decrementing a second digital value by one least significant bit.
The calibration system may include first and second memories that store digital resistance values and digital update values, respectively. Each digital resistance value programs a resistance of a corresponding one of the programmable resistors of the resistor tree. Each digital update value corresponds to one of the digital resistance values. The control logic may adjust a programmable resistor by replacing a digital resistance value in the first memory with a corresponding digital update value from the second memory.
The measurement circuit may include an analog subtractor and a sigma-delta converter. The analog subtractor measures a voltage difference between a selected complementary pair of programmable resistors. The sigma-delta converter provides a bit stream representative of the measured voltage difference. The calibration system may include a counter that counts bits having a predetermined binary value (e.g. 1's or 0's) of the bit stream for a predetermined measurement interval and that provides a sum value. The control logic may include adjust logic that converts the sum value to an adjust value, that increases one digital update value by the adjust value and that decreases a complementary digital adjust value by the adjust value in the second memory for the measurement interval. The adjust logic may include digital compare logic, a digital adder and a digital subtractor. The digital compare logic compares the sum value with predetermined upper and lower thresholds and sets the adjust value to zero if the sum value is within both thresholds, sets the adjust value to one polarity if the upper threshold is reached and sets the adjust value to an opposite polarity if the lower threshold is reached. The digital adder adds the adjust value to a first digital update value and the digital subtractor subtracts the adjust value from a second digital update value that is complementary to the first digital update value.
The control logic may conduct a sequential measurement cycle in which it performs a sequential series of measurement intervals to measure and adjust each complementary pair of programmable resistors of the resistor tree to calibrate the corresponding portion of the resistor ladder. The control logic may be configured to continuously repeat each sequential measurement cycle during operation. Further, the control logic may assert an update signal after each measurement cycle that causes each digital resistance value in the first memory to be replaced by a corresponding digital update value in the second memory. The resistor ladder calibration system may be used for a resistor ladder that is used in a differential manner, where the number of calibrated resistors of the resistor ladder includes half the number of total ladder resistors.
REFERENCES:
patent: 6178388 (2001-01-01), Claxton
patent: 6188346 (2001-02-01), Waho et al.
patent: 6204785 (2001-03-01), Fattaruso et al.
patent: 6459394 (2002-10-01), Nadi et al.
Shu et al., “A 13-b, 10-Msample/ADC Digitally Calibrated with Oversampling Delta-Sigma Converter,” IEEE Journal of Solid-State Circuits, vol. 30, No. 4, Apr. 1995, pp. 443-452, ISSN: 0018-9200/85.
Kwak et al., “A 15-b, 5-Msample/s Low-Spurious CMOS ADC,” IEEE Journal of Solid-State Circuits, vol. 32,
Allen Brian L.
Bacrania Kantilal
Chen Hsin-Shu
Hakkarainen J. Mikko
Sanchez Mario
Intersil America's Inc.
Stanford Gary R.
Wamsley Patrick
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