Calibration method for redundant A/D and D/A converters with a w

Details Calibration method for redundant A/D and D/A converters with a w Calibration method for redundant A/D and D/A converters with a w

1988-12-14

1990-11-13

Shoop, Jr., William M.

Coded data generation or conversion

Converter calibration or testing

341153, 36457101, 36457102, 324130, H03M 110

Patent

active

049705148

ABSTRACT:
A calibration method for redundant A/D and D/A converters with a weighted network and error correction includes performing a self-calibration in which each of n weighted elements is determined as a function of respectively lower weighted elements by means of a measurement with n steps, except for a lowest weighted element. Subsequently each weighted element is calculated and stored in memory in terms of the sum of all of the weighted elements as a function of the results of the measurement with the aid of a calculating register.

REFERENCES:
patent: 4336526 (1982-06-01), Weir
patent: 4399426 (1983-08-01), Tan
patent: 4451821 (1984-05-01), Domogalla
IEEE International Solid-State Circuits Conference, vol. 27, Feb. 22-24, 1984, San Francisco, Conf., pp. 64-65, 319 "Self-Calibrating 12b 12mus CMOS-ADC".
IEEE International Solid-State State Circuits Conference, ISSCC 81/ Feb. 18, 1981, "An Error-Correcting 14b/20 mus CMOS A/D Converter", pp. 62-63.
IEEE Transactions on Circuits and Systems, vol. CAS-30, No. 3, Mar. 1983, "Circuits and Systems Letters", pp. 188-190.
IEEE Transactions on Circuits and Systems, vol. CAS-25, No. 7, Jul. 1978, "Linear Electronic Analog/Digital Conversion Architectures, Their Origins, etc.

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