Calibration circuit of a semiconductor memory device and...

Details Calibration circuit of a semiconductor memory device and... Calibration circuit of a semiconductor memory device and...

2008-05-06

2008-05-06

Phung, Anh (Department: 2824)

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

C365S201000, C365S189050

Reexamination Certificate

active

07369455

ABSTRACT:
A calibration circuit for a semiconductor device and a method of driving the same. The calibration circuit includes a PRBS generator in which a data pattern is generated within an integrated circuit without receiving data from the outside, a PRBS tester that compares output signals of a data latch that strobes and latches an output signal of a data input buffer to determine whether the interlock operation of data and strobe is pass or fail, and a calibration unit that calibrates a delay time using the output signal of the PRBS tester as much as a predetermined unit. Thus, variation in process, voltage, temperature, etc. can be freely calibrated even after package assembly. Accordingly, it is possible to guarantee a set-up/hold value that is necessary for high frequency operation of a system, and to reduce the time and resources necessary for product manufacture and for calibrating these values.

REFERENCES:
patent: 5894081 (1999-04-01), Ashuri
patent: 5996415 (1999-12-01), Stanke et al.
patent: 6182510 (2001-02-01), Stanke et al.
patent: 7019556 (2006-03-01), Yoo
patent: 10173616 (1998-06-01), None
patent: 2003036674 (2003-02-01), None

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