Coded data generation or conversion – Analog to or from digital conversion – Differential encoder and/or decoder
Reexamination Certificate
2011-01-25
2011-01-25
Lauture, Joseph (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Differential encoder and/or decoder
C381S071300
Reexamination Certificate
active
07876250
ABSTRACT:
An analog to digital conversion circuit comprises a first digital noise cancellation filter (16) configured to provide a signal to cancel quantization noise from an analog to digital converted output signal. In a calibration phase a second digital noise cancellation filter (26) is has an input coupled to an input of the first digital noise cancellation filter (16). Mutually different sets of at least one-filter coefficients are programmed in the first and second digital noise canceling filters (16, 26). A difference is computed of averaged size indications of digital output signals derived using signals from the first and second digital noise cancellation filters (16, 26) using the same input signal. Updates of the sets of at least one filter coefficients are adapted dependent on the difference between the averaged size indications.
REFERENCES:
patent: 5272446 (1993-12-01), Chalmers et al.
patent: 5689572 (1997-11-01), Ohki et al.
patent: 5781138 (1998-07-01), Knudsen
patent: 6271781 (2001-08-01), Pellon
patent: 6377196 (2002-04-01), Kolsrud et al.
patent: 6873281 (2005-03-01), Esterberg et al.
patent: 6907374 (2005-06-01), Tsyrganovich
patent: 6970120 (2005-11-01), Bjornsen
patent: 1655841 (2006-05-01), None
Larsson A et al; “A Background Calibration Scheme for Pipelined ADCS Including Non-Linear Operational Amplifier Gain and Reference Error Correction”, SOC Conference 2004. Proceedings. IEEE International, p. 37-40, Sep. 12-15, 2004. Piscataway, NJ, USA, IEEE.
Cauwenberghs G et al; “Adaptive Digital Correction of Analog Errors in Mash ADC'S-Part I: Off-Line and Blind On-Line Calibration”. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing. vol. 47, No. 7. Jul. 2000. pp. 621-628. Piscataway, NJ, USA, IEEE.
Breems L J et al; “A Cascaded Continuous Time Sigma Delta Modulator With 67DB Dynamic Range in 10 MHZ Bandwidth”. IEEE Journal of Solid-State Circuits, vol. 39. No. 12, Dec. 2004. pp. 2152-2160. Piscataway, NJ, USA, IEEE.
Neitola, M et al; “Study of Fully Digital Error Correction in Multibit Delta-Sigma A/D Converters”; 0-7803-7448-7/02, IEEE, pp. 624-.
Larson, L E. et al; “Multibit Oversampled Σ-ΔA/D Convertor With Digital Error Correction”; Electronic Letters, Aug. 4, 1998; vol. 24, No. 16; p. 1051-1052.
Breems Lucien J. M.
Rutten Robert
van der Ploeg Hendrik
Lauture Joseph
NXP B.V.
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