Data processing: measuring – calibrating – or testing – Calibration or correction system – Signal frequency or phase correction
Reexamination Certificate
2000-12-12
2004-01-06
Hoff, Marc S. (Department: 2857)
Data processing: measuring, calibrating, or testing
Calibration or correction system
Signal frequency or phase correction
C702S089000, C702S106000, C702S117000, C702S124000, C324S600000, C324S601000, C324S605000, C324S617000, C714S700000, C713S503000, C327S003000
Reexamination Certificate
active
06675117
ABSTRACT:
This invention relates generally to automatic test equipment for electronics. More particularly, this invention relates to deskewing pairs of single-ended signals so that they can be used as differential signals for testing differential components.
BACKGROUND OF THE INVENTION
Automatic test equipment (ATE) plays a significant role in the manufacture of semiconductor devices. Manufacturers generally use automatic test equipment—or “testers”—to verify the operation of semiconductor devices at the wafer and packaged device stages of the manufacturing process. Manufacturers also use ATE to grade devices for various specifications, for example, speed. Parts can then be labeled and sold according to their tested levels of performance.
FIG. 1
illustrates a highly simplified ATE system. As shown in
FIG. 1
, a host computer
118
runs a test program for testing a DUT
122
via a plurality of pin electronics channels, shown generally as channels
110
a
-
110
e
. The pin electronics channels each have an I/O terminal (
120
a
-
120
e
) for connecting each respective channel to the DUT
122
. Each pin electronics channel typically includes a driver circuit
112
, a detector circuit
114
, and channel overhead circuitry
116
.
The channel overhead circuitry
116
performs numerous functions. It generally includes DACs (digital-to-analog converters) for establishing drive levels for the driver circuit
112
, and DACs for establishing threshold levels for the detector circuit
114
. It also controls the driver circuit
112
to apply signal edges at precisely controlled instants in time, and controls the detector circuit
114
to sample input signals at precisely controlled instants in time. The channel overhead circuitry
116
includes memory for storing digital vectors to be applied to the DUT by the driver circuit
112
and for storing digital states sampled by the detector circuit
114
.
ATE systems have customarily focused on generating single-ended signals accurately. We have recognized, however, that there is also a need for generating differential signals accurately. In contrast with single-ended signals, which convey digital logic by providing one signal referenced to ground, differential signals convey digital logic as differences between two complementary signals, neither of which is ground.
ATE systems have customarily used single-ended hardware for generating differential signals. According to this technique, test systems have employed pairs of drivers to produce single-ended signals that vary as complements of each other. In order to provide timing signals of sufficient accuracy, the single-ended signals must be made to cross each other at or near their respective 50%-points, at the location where they are applied to the DUT. To meet these requirements, a tester must tightly control timing skew.
Conventional test systems have employed processes for reducing timing skew between single-ended channels. These processes have generally involved adjusting variable delay lines to make different driver signals arrive at nodes of the DUT at substantially the same time. One example of these processes is disclosed in U.S. Pat. No. 4,660,197, entitled “Circuitry for synchronizing a multiple channel circuit tester,” assigned to Teradyne, Inc., of Boston, Mass.
We have recognized that conventional processes for reducing skew (or “deskewing”) suffer from small but significant errors. For example, conventional deskewing processes employ a channel's detector for measuring the delay of the channel's corresponding driver. We have found that small differences in threshold levels between different detectors introduce timing errors that affect deskewing accuracy. Because driver edges have finite slew rates, errors in threshold levels translate into timing errors, causing the detectors to misreport the time at which driver edges occur.
In addition, detector circuits themselves have skew. Although most test systems provide processes for deskewing detectors, skew remaining between detectors adds to driver skew and thus degrades driver accuracy. The combination of these errors may be too great to ensure that differential signals generated by the drivers cross at or near their 50%-points.
SUMMARY OF THE INVENTION
With the foregoing background in mind, it is an object of the invention to reduce timing skew between single-ended signals used to generate differential signals more accurately than is possible using conventional techniques.
To achieve the foregoing object and other objectives and advantages, a measurement circuit is coupled to the outputs of first and second driver circuits. The measurement circuit has a first input coupled to the output of the first driver circuit and a second input coupled to the output of the second driver circuit. Each of the first and second driver circuits is made to generate an edge. The edges from the drivers propagate toward non-terminated loads at the DUT and to the measurement circuit, where they cause the first and second inputs of the measurement circuit to each undergo a first voltage step. When the edges encounter their respective non-terminated loads at the DUT, they reflect back toward the measurement circuit, where they cause the first and second inputs to each undergo a second voltage step. The time difference between the first and second voltage steps is then measured for both inputs of the measurement circuit. In response to the time differences, a delay of at least one of the first and second driver circuits is adjusted to substantially equalize the arrival times of edges from the first and second driver circuits to the DUT. Because one circuit (i.e., the measurement circuit) measures the delay from both drivers, errors associated with using two detector circuits are eliminated and more accurate results are obtained.
REFERENCES:
patent: 4660197 (1987-04-01), Wrinn et al.
patent: 5058087 (1991-10-01), Welzhofer et al.
patent: 5661427 (1997-08-01), McBride et al.
patent: 5905967 (1999-05-01), Botham
patent: 5982827 (1999-11-01), Duffner et al.
patent: 6052810 (2000-04-01), Creek
patent: 6133725 (2000-10-01), Bowhers
patent: 6281699 (2001-08-01), Bishop
patent: 0390562 (1990-10-01), None
U.S. patent application Ser. No. 09/427433, Hauptman et al., filed Oct. 26, 1999.
Adam Sean P.
Bowhers William J.
Desta Elias
Rubenstein Bruce D.
Teradyne, Inc.
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