Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2011-08-16
2011-08-16
Donovan, Lincoln (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S149000
Reexamination Certificate
active
07999585
ABSTRACT:
Devices and methods for varying individual periods or cycle times of upconverted clock signals within a corresponding reference clock cycle are disclosed. In some embodiments, these varying cycle times may improve signal synchronization between the upconverted clock and the reference clock. In different embodiments, different types of counters and counting circuits keep track of the number of elapsed upconverted clock cycles in order to determine the specific upconverted clock cycles with longer cycle times. In some embodiments, a signal may be sent to a delay line to change the amount of delay between upconverted clock pulses, thereby increasing or decreasing a specific upconverted clock cycle time or period. In some embodiments the specific upconverted clock cycle(s) changed in each reference clock cycle may vary, which may further improve reconciliation between the upconverted clock cycles and the corresponding reference clock cycle.
REFERENCES:
patent: 5465076 (1995-11-01), Yamauchi et al.
patent: 6208183 (2001-03-01), Li et al.
patent: 6292040 (2001-09-01), Iwamoto et al.
patent: 7095261 (2006-08-01), Drexler et al.
patent: 7190201 (2007-03-01), Haerie et al.
patent: 7368965 (2008-05-01), Drexler et al.
patent: 7423462 (2008-09-01), Drexler et al.
patent: 7423463 (2008-09-01), Drexler et al.
patent: 7489171 (2009-02-01), Song
patent: 7495487 (2009-02-01), Ma et al.
patent: 7583119 (2009-09-01), Song
patent: 7619453 (2009-11-01), Ma et al.
patent: 7671648 (2010-03-01), Kwak
patent: 7812593 (2010-10-01), Lin et al.
patent: 2002/0041196 (2002-04-01), Demone et al.
patent: 2006/0033544 (2006-02-01), Hul et al.
patent: 2008/0123445 (2008-05-01), Vergnes et al.
patent: 2008/0205550 (2008-08-01), Rofougaran
patent: 2008/0246520 (2008-10-01), Ma et al.
patent: 2009/0146712 (2009-06-01), Ma et al.
patent: 2010/0134166 (2010-06-01), Kwak
patent: 2010/0156459 (2010-06-01), Plants et al.
patent: 2010/0321076 (2010-12-01), Bae et al.
patent: 2011/0002181 (2011-01-01), Rhee et al.
Helal et al., “A Highly Digital MDLL-Based Clock Multiplier That Leverages a Self-Scrambling Time-to-Digital Converter to Achieve Subpicosecond Jitter Performance”, IEEE Journal of Solid-State Circuits, 43(4): 855-863.
PCT International Search Report and Written Opinion from PCT/US10/37175, mailed on Aug. 11, 2010.
Chen Jianrong
Kapusta Ronald A.
Lin Doris
Analog Devices Inc.
Donovan Lincoln
Houston Adam D
Kenyon & Kenyon LLP
LandOfFree
Calibrating multiplying-delay-locked-loops (MDLLS) does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Calibrating multiplying-delay-locked-loops (MDLLS), we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Calibrating multiplying-delay-locked-loops (MDLLS) will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2659936