Calibrated automatic test system

Details Calibrated automatic test system Calibrated automatic test system

1986-07-22

1988-02-09

Karlsen, Ernest F.

Electricity: measuring and testing

Plural, automatically sequential tests

324 73AT, 324 74, 371 20, 371 25, G01R 3100, G01R 3128

Patent

active

047243783

ABSTRACT:
A calibrated automatic test system includes a test station for generating digital test function codes and a test head containing a plurality of I/O pins for connection to a device under test. Each I/O pin includes a pin electronics circuit responsive to the digital test function codes for providing test signals to the device under test. The pin electronics circuits are inexpensive CMOS IC's and lack the accuracy needed to test VLSI devices at the frequencies of interest. An external calibration unit is connected to each I/O pin and data measurements are taken which represent the performance of the CMOS IC's. The data measurements are converted to calibrated function codes representing desired data values which are then stored in correction memory circuits which respond to nominal digital test function codes and substitute in their places calibrated function codes which are then supplied to the pin electronics circuits.

REFERENCES:
patent: 4099240 (1978-07-01), Rode et al.
patent: 4125763 (1978-11-01), Drabing et al.
patent: 4354268 (1982-10-01), Michel et al.
patent: 4590422 (1986-05-01), Milligan
patent: 4635256 (1987-01-01), Herlein
patent: 4637020 (1987-01-01), Schinabeck

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