Calibratable field effect transistors

Details Calibratable field effect transistors Calibratable field effect transistors

1998-08-13

2001-01-30

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

C327S543000

Reexamination Certificate

active

06181194

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to field effect transistors and is applicable in particular, though not necessarily, to field effect transistors for use in current mirrors and other current sources.
BACKGROUND OF THE INVENTION
In many analogue circuit arrangements there is a requirement for accurate and constant reference voltages and currents. In the case of reference currents, these are often generated using a reference voltage source and a resistor. In integrated analogue circuits, chip space is at a premium and it is common to integrate only one, or a small number of such source/resistor combinations into a chip and to generate other reference currents from the basic reference current(s) using current mirrors. Current mirrors have a relatively simple construction and do not occupy a large chip area. A typical current mirror, comprising a pair of matched MOSFET transistors (a reference transistor T and a mirroring transistor M), is illustrated in
FIG. 1
where t
n
is the reference current and lout is the mirrored output current. The current mirror may be extended by adding one or more additional current mirroring transistors in parallel.
One application for current mirrors is in digital to analogue (D/A) converters, where inaccuracies in the reference currents and voltages tend to dominate as a source of conversion errors over factors such as switch resistances and unmatched loads. A simple 4-bit D/A converter is shown in
FIG. 2
, and comprises a reference MOSFET transistor T and four mirroring MOSFET transistors M
0
to M
3
arranged in a current mirroring configuration. Transistors T and M
0
have a channel width to length ratio of W/L whilst transistors M
1
, M
2
, and M
3
have ratios of 2W/L, 4W/L, and 8W/L respectively. A switch (S
0
to S
3
) is arranged in series with the drain of each MOSFET (M
0
to M
3
), the switches being controlled by respective bits (a
0
to a
3
) of the digital (binary) signal to be converted. a
0
corresponds to the least significant bit (LSB) of the signal whilst a
3
corresponds to the most significant bit (MSB). The switches (S
0
to S
3
) are coupled together at one end and draw an output current I
out
depending upon the activation state of the switches.
Current mirrors such as that employed in the D/A converter of
FIG. 2
copy or scale reference currents with varying degrees of accuracy depending upon the precise construction of the mirrors. In practice, errors will arise because the transistors of the current mirror are not identical (or are not scaled identically). The extent of this mismatch may be minimised by using the common-centroid method to determine the layout of the transistors. For example, for the 4-bit converter shown in
FIG. 2
, transistors T and M
0
are provided by respective single transistor elements, whilst transistors M
1
, M
2
, and M
3
are provided respectively by two, four, and eight parallel connected transistor elements (each with a channel width to length ratio of W/L). These elements are arranged in a geometric pattern as illustrated in
FIG. 3
where transistor elements are shown by element number (and T represents the diode connected reference transistor). However, particularly for high bit D/A converters (e.g. 12 or 14 bits), the common centroid method does not ensure high accuracy for conversion of the MSBs. This may be due to the large separation between transistor elements making up the transistors corresponding to these bits. Whilst techniques such as laser trimming can be used to physically adjust the dimensions and properties of certain circuit elements, these are generally time consuming and expensive to implement.
There are many other applications where inaccuracies in the properties of field effect transistors can be a source of serious error. One example is the so called ‘pipeline’ analogue to digital (A/D) converters in which field effect transistors are incorporated into subtractor, multiplier, and comparator circuits. The precision of such a converter is critically dependent upon the
30
operating precision of the transistors in these circuits.
In high quality applications D/A and A/D converters must be capable of operating at the Nyquist frequency. In the case of mobile communication devices, at present and near future data processing rates, use of converters in the intermediate-frequency (IF) band means an operating frequency of 10 MHz or greater. Whilst converters based upon the architecture of
FIG. 2
can operate at such high frequencies, the conversion accuracy is often unsatisfactory for high bit converters. On the other hand, converters based on alternative architectures, such as the sigma-delta (or oversampling) converter, offer high accuracy and high bit conversion but suffer from slow speed (operating at only a few MHz). With these or other converters, the large chip area occupied by the converter as well as high power consumption can also become a problem where large scale integration is desired.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide for the calibration of field effect transistors using electrical adjustment.
According to a first aspect of the present invention there is provided an electrical circuit comprising:
a field effect transistor having a source, a drain, and a gate; and
a calibration DC current source and a calibration DC current sink coupled to respective spaced apart regions of the transistor gate, whereby in use a substantially DC calibration current may be passed through the gate between said spaced apart regions.
The present invention provides for trimming of the ‘effective’ width of the channel of a field effect transistor using a DC calibration current. The calibration current affects the properties of the channel to a small extent, relative to the size of the calibration current, and it is therefore possible to adjust, or trim, the channel to a marginal extent using relatively large variations in the calibration current.
Preferably, the transistor gate is resistive, for example resistive polysilicon. More preferably, the gate material is unsilicided polysilicon. Typically, the resistance of the gate is greater than 10 ohm/□(ohms/squre). Preferably, the calibration current source and sink have high output impedances, for example greater than 200 K ohms.
Preferably, the calibration current source and sink are arranged to source and sink substantially identical DC currents. In this way, interference of the calibration current with the active signal current of the transistor is prevented. More preferably, the calibration source and sink are provided by a digital to analogue converter coupled to respective gate regions via a current mirror.
The field effect transistor may be composed of a plurality of transistor elements coupled together, with a common gate or a set of serially connected gates. In this case, said two spaced apart regions may be provided on the gate, or gate region, of one of the transistor elements. Alternatively, a first of the spaced apart regions may be provided on a first of the gates or gate regions with the other spaced apart region being provided on a second of the gates or gate regions. Said first and second gate regions may be coupled in series about a resistive element. Additional gate regions and respective resistive elements may be coupled in series between the first and second gate regions. In yet another alternative, independent calibration DC current sources and sinks may be coupled to respective spaced apart regions of two or more gates or gate regions, whereby the corresponding transistor elements may be independently calibrated.
According to a second aspect of the present invention there is provided a current mirror comprising:
a reference field effect transistor and at least one mirroring field effect transistor, at least one of the transistors being arranged in an electrical circuit according to the above first aspect of the present invention; and
a constant current source coupled to the reference transistor, wherein in use the reference current causes a mir

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