Calendar queue cache

Details Calendar queue cache Calendar queue cache

1999-12-16

2003-05-06

Ton, Dang (Department: 2666)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C370S229000

Reexamination Certificate

active

06560238

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a calendar queue for enforcing quality of service action specs and, in particular, to a calendar queue that utilizes a fast lookup logic to speed the process of filling and emptying the cache.
BACKGROUND
In one type of policy network, a Calendar Queue is used to schedule the output packets after policy enforcement according to the corresponding bandwidth (QoS Action Spec) which specifies when and how often the packets should depart. Conventionally, the mechanism is based on a queue that includes a plurality of equally spaced time slots. One timeslot represents one bandwidth unit. If the queue is implemented by hardware, then one time slot can be one external memory location, with these slots being contiguous external memory space. The operation is shown in FIG.
1
.
When the packet for a given QoS Action Spec leaves the system, the conventional system first invalidates the current slot and advances to the new slot for next schedule after a bandwidth interval. If the new slot turns out to be valid (occupied by another QoS Action) then the system searches for the nearest invalid slot after the occupied one to schedule the next packet. In
FIG. 1
, the QoS Action Spec #
20
that has a bandwidth equal to 2 represents this case.
The Action Spec #
20
, according its bandwidth, should be inserted to the time slot
2
. But since the slot
2
has been occupied by the Action Spec #
21
then the available slot
3
is selected. Checking the valid bit and searching the first available invalid bit involve a lot of memory access operations. Use of external memory creates a long latency for scheduling the packets. Even worse, if the memory is also shared by other processors, the arbitration time can make the latency even longer.
SUMMARY
The present invention is a method of scheduling packet output in accordance to a quality of service (QoS) action specification. A calendar queue of bandwidth timeslots is maintained, wherein the bandwidth timeslots are organized into groups. Look-up logic circuitry is invoked that inspects the bandwidth timeslots of a group in the queue substantially simultaneously. The look-up logic circuitry determines from the group a first unoccupied bandwidth timeslot in which a current packet can be scheduled and also determines from the group a first occupied bandwidth timeslot which contains a next packet to transmit.


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