Calendar clock caching in a multiprocessor data processing syste

Details Calendar clock caching in a multiprocessor data processing syste Calendar clock caching in a multiprocessor data processing syste

1998-09-17

2000-04-18

Peikari, B. James

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Combined with diverse art device

708111, 713502, 711144, 711156, G06F 114, G06F 1208

Patent

active

060527005

ABSTRACT:
Each processor (92) in a data processing system (80) caches a copy of the master calendar clock (97). The master calendar clock (97) and all of the cached calendar clocks (272) are periodically incremented utilizing a common clock (99). Whenever a processor (92) in the system (80) loads the master calendar clock (97) with a new value, that processor (92) broadcasts a cached calendar clock updated interrupt signal (276) to all of the processors in the system. In response to this interrupt (278), each processor (92) clears its cached calendar clock valid flag (274). Whenever a read calendar clock instruction is executed on a processor (92), the flag (274) is tested, and if set, its cached calendar clock (272) value is returned. Otherwise, the master calendar clock (97) value is retrieved, written to that processor's cached calendar clock (272), and returned. The cached calendar clock valid flag (274) is set to indicate a valid cached calendar clock (272).

REFERENCES:
patent: 4590550 (1986-05-01), Eilert et al.
patent: 5444780 (1995-08-01), Hartman, Jr.
patent: 5761683 (1998-06-01), Logan et al.
patent: 5852824 (1998-12-01), Brown

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