CAcT-Tg (CATT) low voltage NVM cells

Details CAcT-Tg (CATT) low voltage NVM cells CAcT-Tg (CATT) low voltage NVM cells

2007-05-29

2007-05-29

Tran, Michael (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C257S315000

Reexamination Certificate

active

11506119

ABSTRACT:
Described herein are the methods the CACT and TG Non-volatile program erase methods, for programming and erasing NVM cells. This combination allows use of low voltage methods for program, and erases. The typical cell described uses the “Channel Accelerated Carrier Tunneling (CACT) method for programming memories” for accumulating one type of carriers in the floating gate, and another method, the Tunnel Gun (TG) method, for accumulating the other type of carriers in the floating gate of the cells. These methods use low applied voltages to program and erase the Non-Volatile Memory cell. The proposed CATT (CAcT-Tg) cells by elimination of high voltage requirements are scalable with technology and easily manufacturable using current processes technologies. These cells also have multi-bit storage capability as the program erase methods used are self-limiting in character. Another advantage is the increase in reliability of Cells using this method due to reduced voltage stress.

REFERENCES:
patent: 6388293 (2002-05-01), Ogura et al.
patent: 6538925 (2003-03-01), Miida
patent: 2006/0240613 (2006-10-01), Wang

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