Cached subtractive decode addressing on a computer bus

Multiplex communications – Wide area network – Packet switching

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395298, 370 8513, G06F 1202

Patent

active

055686214

ABSTRACT:
A local bus subtractive decode device that improves the speed of its subtractive decoding by storing or caching subtractively decoded addresses. At the start of subsequent address cycles, this cached subtractive decode device compares the address and command on the local bus with the stored addresses and commands, and if it finds a match, claims the transaction as would a positive decode device. It can do so without conflict because no positive decode device will be claiming the transaction.

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Peripheral Component Interconnect (PCI), Revision 1.0 Specification, PCI Special Interest Group (Jun. 22, 1992).
Changes to PCI Specification, Rev. 1.0, Part 2, Preliminary, PCI Special Interest Group (1992).

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