Cache which provides status information

Details Cache which provides status information Cache which provides status information

1989-04-17

1991-11-19

Bowler, Alyssa H.

Static information storage and retrieval

Magnetic bubbles

Guide structure

36523001, 365 49, G06F 700, G06F 704, G06F 720, G11C 800

Patent

active

050670786

ABSTRACT:
A first processing system is coupled to a plurality of integrated circuits along a P bus. Each of these integrated circuits has a combination cache and memory management unit (MMU). The cache/MMU integrated circuits are also connected to a main memory via an M bus. A second processing system is also coupled to the main memory primarily via a secondary bus but also via the M bus. External TAGs coupled between the M bus and the secondary bus are used to maintain coherency between the first and second processing systems. Each external TAG corresponds to a particular cache/MMU integrated circuit and maintains information as to the status of its corresponding cache/MMU integrated circuit. The cache/MMU integrated circuit provides the necessary status information to its corresponding external TAG in a very efficient manner. Each cache/MMU integrated circuit can also be converted to a SRAM mode in which the cache performs like a conventional high speed static random access memory (SRAM). This ability to convert to a SRAM provides the first processing system with a very efficient scratch pad capability. Each cache/MMU integrated circuit also provides hit information external to the cache/MMU integrated circuit with respect to transactions on the P bus. This hit information is useful in determining system performance.

REFERENCES:
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patent: 4219883 (1980-08-01), Kobayashi et al.
patent: 4264953 (1981-04-01), Douglas et al.
patent: 4357656 (1982-11-01), Saltz et al.
patent: 4464717 (1984-08-01), Keeley et al.
patent: 4819154 (1989-04-01), Stiffler et al.
patent: 4953073 (1990-08-01), Moussouris et al.

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