Cache testing using a modified snoop cycle command

Details Cache testing using a modified snoop cycle command Cache testing using a modified snoop cycle command

1995-02-23

1997-03-18

Swann, Tod R.

395445, G06F 1202

Patent

active

056130872

ABSTRACT:
The cache controller of a second level cache in an Intel Pentium processor based computer system contains test circuitry that allows reading and writing directly into all tag RAM databit locations. This circuitry responds to a modified External Address Strobe (EADS#) command to invoke the tag test cycle. The EADS# command is normally used in a SNOOP read cycle by the system. In a SNOOP cycle, the main memory controller invokes the EADS# command to request the first level (L.sub.1) and second level (L.sub.2) caches for modified information stored in those caches. In the tag test cycle the EADS# command line is held down twice as long as it would in a normal SNOOP read Cycle. Because of its added length, the SNOOP cycle circuits in the L.sub.2 cache ignore the command on the EADS# command line. However, the tag RAM test circuitry in the L.sub.2 cache recognizes the extended EADS# strobe providing a path to access all bit locations in a tag RAM for both read and write cycles to test the tag RAM or to load those bit positions to selected states in testing other portions of the cache.

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IBM Technical Disclosure Bulletin No. 9B, vol. 36, pp. 197-198, Sep. 1993, entitled "Cache Tag RAM Diagnostic Mode" by Ferrarini et al.
IBM Technical Disclosure Bulletin No. 5A, vol. 32, pp. 126-128, Oct. 1989 entitled "Intel 82385 Snoop Diagnostic Circuit to Test DMA/BUS Master Snoop Cycles" by Begun et al.

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